IDT77V400S156BCG IDT, Integrated Device Technology Inc, IDT77V400S156BCG Datasheet - Page 3

• Manufacturer Part Number: IDT77V400S156BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V400S156BCG

IDT77V400
To DRAM
IP0D0-3
IP1D0-3
IP2D0-3
IP3D0-3
IP4D0-3
IP5D0-3
IP6D0-3
IP7D0-3
IFRM0-7
ICLK0-7
ABYTE
SBYTE
byte 0
Cntl.
BYTE-PUT-PROTECT
4
4
4
4
4
4
4
4
8
8
.
BYTE
byte 1
32
[first word]
INPUT EDIT BUFFER
and ICLK
Control
Latches
Buffers
Config.
IFRM
Config.
Input
and
CLEAR
TRANSFER BUS
byte 2
IOD BUS Bits 0 - 31
Cntl.
Bits 0-71
INPUT
32
byte 3
4
4
4
MUX
4
4
4
4
4
4
Random Access Cell Memory
(from ISAM)
[second word]
32
32
Config.
Figure 3 Input and Output Edit Buffer Block Diagram
Pointer Decode + Control
Pointer Decode + Control
(8192 ATM Cells)
Nibble Counters,
Buffer Memory
Output SAM Port 0
Output SAM Port 6
Output SAM Port 7
Input SAM Port 0
Input SAM Port 1
Input SAM Port 7
Nibble Counters
Figure 2 Functional Block Diagram
CRC
GEN
CRC error
COMPARE
8
8
HEC
8
DRAM BUS
3 of 26
OUTPUT
Bits 0-71
Edit Buffer
Input
Output
Header
Addr
1
1
CTLEN
72
Port
Status
32
RESET
4
4
4
32
4
4
4
[first word]
OR - P/P
Memory
Control
Config.
Logic
Edit Buffer
Config.
CS
Output
OUTPUT EDIT BUFFER
Cntl.
Control Interface and
32
Command Control
OE
4
4
4
CRC Logic
SCLK
Edit Buffer
Control
Configuration
TRANSFER BUS
ADDR0-3
Register
and OCLK
Register
Register
Status
OFRM
Control
Error
Output
Latches
Buffers
OUTPUT
Bits 0-71
Refresh
Control
Mode Control
and
CMD0-5
4
MUX
8
and CRC
6
IOD0-31
[second word]
OR - HEADER
32
32
32
8
(to OSAM)
8
8
4
4
4
4
4
4
4
4
CRCERR
IOD0-31
8
OCLK0-7
OP0D0-3
OP1D0-3
OP2D0-3
OP3D0-3
OP4D0-3
OP5D0-3
OP6D0-3
OP7D0-3
OFRM0-7
CRC
GEN
3606 drw 03
HEC
XOR
8
3606 drw 02
March 31, 2001