IDT77V400S156BC IDT, Integrated Device Technology Inc, IDT77V400S156BC Datasheet
IDT77V400S156BC
Specifications of IDT77V400S156BC
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IDT77V400S156BC Summary of contents
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Features List Features List Features List Features List Single chip supports port switch at 155Mbps per ! port Central Memory Architecture eliminates Head-of-Line ! Blocking by sharing the memory array with all ports Low power dissipation ...
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IDT77V400 Description Description Description Description The IDT77V400 ATM Cell Based Switching Memory provides the logic and memory necessary to perform high-speed buffering and switching operations on ATM cell data. A single IDT77V400 provides a cost effective switching element to implement ...
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IDT77V400 SBYTE Config. Cntl. Cntl. 4 IP0D0 IP1D0 IP2D0-3 Input 4 4 Latches IP3D0-3 4 and 4 Buffers 4 IP4D0-3 4 IP5D0-3 4 IP6D0 IP7D0 IFRM ICLK0-7 and ICLK 8 ...
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IDT77V400 Package Diagram Package Diagram Package Diagram Package Diagram All V /V pins must be connected to power supply. All V CC CCQ 28mm x 3.4mm VCC 3 VSS 4 VSS 5 IOD0 6 IOD1 7 IOD2 ...
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IDT77V400 (1,2,3) (1,2,3) (1,2,3) (1,2,3) Package Diagram Package Diagram Package Diagram Package Diagram ABYTE 6D1 6D3 IOD SBYTE 6D0 6D2 C1 ...
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IDT77V400 Pin Description - PQFP Package Pin Description - PQFP Package Pin Description - PQFP Package Pin Description - PQFP Package Pin Number Symbol Type 132 SCLK I 139 CS I 133-138 CMD0 166 RESET I ...
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IDT77V400 Pin Number Symbol Type 94 CTLEN I 206 ABYTE I 207 SBYTE I 1, 52-54, 104-06, NC — 156-59 2, 15-16, 41-42, 49- VCC Power 50, 56, 67-68, 83-84, 101-02, 108, 119-20, 126, 140, 154, 165, 184, 193, 204 ...
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IDT77V400 Pin Number Symbol Type A11-13, B11-13, ICLK0-7 I C12-13 A9-10, B9-10,C8-11 IFRM0-7 I A3-8, A15-16, B3-8, IP(0-7)D(0-3) I B14-16, C4-7, C14-16, D14-16, E14-16, F15-16 P10-12, R10-11, OCLK0-7 I T10-12 P7-9, R8-9, T7-9 OFRM0-7 I/O K15, L14-16,M14-16, OP(0-7)D(0-3) O N1-2, ...
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IDT77V400 Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Symbol 2 V Terminal Voltage with Respect to V TERM T Temperature Under Bias BIAS T Storage Temperature STG I DC Output Current OUT 1. Stresses greater ...
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IDT77V400 DC Electrical Characteristics Over the Operating Temperature and Supply DC Electrical Characteristics Over the Operating Temperature and Supply DC Electrical Characteristics Over the Operating Temperature and Supply DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Voltage ...
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IDT77V400 Symbol t CS Hold Time after SCLK High HC t CMD Setup Time to SCLK High SCM t CMD Hold Time after SCLK High HCM t IOD Setup Time to SCLK High SIO t IOD Hold Time after SCLK ...
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IDT77V400 Basic Functional Description Basic Functional Description Basic Functional Description Basic Functional Description Input data is received by the Switching Memory via the four-bit input data ports (IPxD). Each input port is configured as a double buffer with SRAM storage ...
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IDT77V400 Control Interface Commands Control Interface Commands Control Interface Commands Control Interface Commands 1 Command GPIx Get Pre/Post Pend Data from ISAMx GHIx Get Header from ISAMx GPE Get Pre/Post Pend Data from Edit Buffer GHE Get Header from Edit ...
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IDT77V400 Control Enable Timing Waveform Control Enable Timing Waveform Control Enable Timing Waveform Control Enable Timing Waveform The CTLEN bit of the configuration register (Bit 31) is LOW for this waveform. If the CTLEN bit of the configuration register is ...
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IDT77V400 Input Ports Input Ports Input Ports Input Ports A 155Mbps input Data Path Interface (DPI) consists of six pins – four data bits (IPxD0-3), an input clock (ICLKx), and an input framing signal (IFRMx). A further definition of the ...
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IDT77V400 The OFRM pin is always monitored internally by the Switching Memory. The OFRMx output is released to a High-impedance state when cell bus mode and a cell is not ready for dispatch. Upon receiving a HIGH ...
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IDT77V400 SCLK CS REFRESH CMD0-5 IOD0-31 IOD BUS Input Input MODE 1 The Refresh sequence begins with the REF command and ends when the four cycle Buffer Memory Refresh has completed. 2 REFRESH command can only be valid for one ...
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IDT77V400 SCLK LOAD GET CMD0-5 OR HEADER OSAM STATUS Cell Header IOD0-31 Address Data IOD BUS Input Input MODE Figure 11 Multi-Sequence Functional Waveform Example - Load, Memory Store, Initiate Refresh Low. 2 The 13-bit cell address ...
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IDT77V400 Port Configuration Codes Port Configuration Codes Port Configuration Codes Port Configuration Codes Config 1,2 Code MSb LSb 0 0000 4 bit 0001 8 bit, CLK/FRM 0 3 0010 4 bit 0011 8 bit, CLK/FRM 0 3 0100 4 bit ...
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IDT77V400 Status Register Definition Status Register Definition Status Register Definition Status Register Definition Register ISAM ISAM Port 1 Bit Full Error IOD0 0 X — IOD1 0 — X IOD2 1 X — IOD3 1 — X IOD4 2 X ...
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IDT77V400 Edit Buffer Protect/Clear Codes Edit Buffer Protect/Clear Codes Edit Buffer Protect/Clear Codes Edit Buffer Protect/Clear Codes Mode Byte ...
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IDT77V400 Cell Alignment Options Cell Alignment Options Cell Alignment Options Cell Alignment Options Cell Configuration No Pre/Post Pend Data 1 byte prepended 1 byte postpended 2 bytes prepended 1 byte prepended and 1 byte postpended 2 bytes postpended 3 bytes ...
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IDT77V400 77V400 Package Drawing — 208-pin PQFP 77V400 Package Drawing — 208-pin PQFP 77V400 Package Drawing — 208-pin PQFP 77V400 Package Drawing — 208-pin PQFP March 31, 2001 ...
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IDT77V400 — — — — 77V400 Package Drawing 77V400 Package Drawing 77V400 Package Drawing 77V400 Package Drawing Page Two Page Two Page Two Page Two March 31, 2001 ...
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IDT77V400 77V400 Package Drawing — 256-pin BGA 77V400 Package Drawing — 256-pin BGA 77V400 Package Drawing — 256-pin BGA 77V400 Package Drawing — 256-pin BGA March 31, 2001 ...
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IDT77V400 Ordering Information Ordering Information Ordering Information Ordering Information IDT XXXXX A 999 Device Power Speed Type Datasheet Document History Datasheet Document History Datasheet Document History Datasheet Document History 3/1/99: Updated to new format. Added Industrial Specifications. Added S156 Speed ...