IDT72V51243L6BB IDT, Integrated Device Technology Inc, IDT72V51243L6BB Datasheet - Page 28

• Manufacturer Part Number: IDT72V51243L6BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51243L6BB

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 3.7ns
• Word Size: 18b
• Organization: 8Kx18x4
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51243L6BB

NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Serial Enable
Serial Input
Serial Clock
Default Mode
DFM = 0
Master Reset
Active Bus
Active Bus
PAE-Qx
PAF-Qx
WADEN
WRADD
RADEN
RDADD
WCLK
RCLK
WEN
REN
PAF
PRS
PAE
OV
FF
(5)
(6)
SENI
SI
DFM
t
t
QS
AS
MQ1
SCLK
t
AS
t
QS
Qx
w-2
MRS
SENO
Qx
r-2
t
SO
QH
Figure 6. Serial Port Connection for Serial Programming
t
AH
t
QH
t
AH
w-1
SENI
SI
DFM
r-1
t
PRSS
t
Figure 5. Partial Reset
ENS
t
PRSS
MQ2
SCLK
t
ENS
w
MRS
SENO
28
SO
r
t
PRSH
t
PRSH
w+1
r+1
t
WFF
w+2
SENI
SI
DFM
r+2
t
MQn
WAF
t
ENS
SCLK
t
t
ROV
RAE
t
ENS
COMMERCIAL AND INDUSTRIAL
MRS
w+3
SENO
SO
r+3
TEMPERATURE RANGES
t
PAF
t
PAE
5937 drw09
5941 drw10
Serial Loading
Complete