IDT72V51543L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51543L7-5BB8 Datasheet - Page 25

• Manufacturer Part Number: IDT72V51543L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51543L7-5BB8

• Configuration: Dual
• Density: 1Mb
• Access Time (max): 4ns
• Word Size: 18b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51543L7-5BB8

the new quadrant selected 1 RCLK cycle after quadrant selection. PAEn[0:7]
gets status of queues, Queue[0:7] respectively.
“xxxxxx01”. PAEn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the RDADD address is “xxxxxx10”.
PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the RDADD address is “xxxxxx11”. PAE[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs PAE[2:7] will
be don't care states.
queue ‘x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra RCLK cycle delay before that queues status is
correctly shown on the respective output of the PAEn bus.
on the PAEn bus can change every RCLK cycle. Also, data can be read out
of a queue on the same RCLK rising edge that a quadrant is being selected,
the only restriction being that a read queue selection and PAEn quadrant
selection cannot be made on the same RCLK cycle.
output on PAE[0:7] constantly.
device the PAEn busses of all devices are connected together, when switching
between quadrants of different devices the user must utilize the 3 most significant
bits of the RDADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
information. Also refer to Table 2, Read Address Bus, RDADD.
PAEn – POLLED BUS
mode. In polled mode the PAEn bus automatically cycles through the 4
IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
To address the second quadrant, Queue[8:15], the RDADD address is
Note, that if a read or write operation is occurring to a specific queue, say
Quadrants can be selected on consecutive clock cycles, that is the quadrant
If 8 or less queues are setup then queues, Queue[0:7] have their PAE status
When the multi-queue devices are connected in expansion of more than one
Please refer to Figure 22, PAE n - Direct Mode Quadrant Selection for timing
If FM is HIGH at master reset then the PAEn bus operates in Polled (looped)
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quadrants within the device regardless of how many queues have been setup
in the part. Every rising edge of the RCLK causes the next quadrant to be loaded
on the PAEn bus. The device configured as the master (MAST input tied HIGH),
will take control of the PAEn after MRS goes LOW. For the whole RCLK cycle
that the first quadrant is on PAEn the ESYNC (PAEn bus sync) output will be
HIGH, for all other quadrants, this ESYNC output will be LOW. This ESYNC
output provides the user with a mark with which they can synchronize to the
PAEn bus, ESYNC is always HIGH for the RCLK cycle that the first quadrant
of a device is present on the PAEn bus.
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the PAEn bus and
will place its first quadrant on the bus on the rising edge of RCLK after the MRS
input goes LOW. For the next 3 RCLK cycles the master device will maintain
control of the PAEn bus and cycle its quadrants through it, all other devices hold
their PAEn outputs in High-Impedance. When the master device has cycled all
of its quadrants it passes a token to the next device in the chain and that device
assumes control of the PAEn bus and then cycles its quadrants and so on, the
PAEn bus control token being passed on from device to device. This token
passing is done via the EXO outputs and EXI inputs of the devices (“PAE
Expansion Out” and “PAE Expansion In”). The EXO output of the master device
connects to the EXI of the second device in the chain and the EXO of the second
connects to the EXI of the third and so on. The final device in a chain has its EXO
connected to the EXI of the first device, so that once the PAEn bus has cycled
through all quadrants of all devices, control of the PAEn will pass to the master
device again and so on. The ESYNC of each respective device will operate
independently and simply indicate when that respective device has taken control
of the bus and is placing its first quadrant on to the PAEn bus.
the EXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAEn bus.
When devices are connected in expansion mode, only one device will be
Please refer to Figure 27, PAE n Bus – Polled Mode for timing information.
When operating in single device mode the EXI input must be connected to
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES