IDT89HPES24N3YCBXG IDT, Integrated Device Technology Inc, IDT89HPES24N3YCBXG Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES24N3YCBXG
• Description: IC PCI SW 24LANE 3PORT 420-SBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24N3YCBXG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES24N3YCBXG

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES24N3 Data Sheet
The following tables list the functions of the pins provided on the PES24N3. Some of the functions listed may be multiplexed onto the same pin.
PEREFCLKP[1:0]
PEREFCLKN[1:0]
PEARP[7:0]
PEARN[7:0]
PEBRP[7:0]
PEBRN[7:0]
PECRP[7:0]
PECRN[7:0]
PECTN[7:0]
PEATP[7:0]
PEBTP[7:0]
PEBTN[7:0]
PECTP[7:0]
PEATN[7:0
REFCLKM
PEALREV
PEBLREV
PECLREV
Signal
Type
O
O
O
I
I
I
I
I
I
I
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PCI Express Port B Serial Data Receive. Differential PCI Express receive
pairs for port B.
PCI Express Port B Serial Data Transmit. Differential PCI Express trans-
mit pairs for port B
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
3 of 30
Name/Description
December 18, 2007