IDT89HPES16T4G2ZABX8 IDT, Integrated Device Technology Inc, IDT89HPES16T4G2ZABX8 Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES16T4G2ZABX8
• Description: IC PCI SW 16LANE 4PORT 288-SBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4G2ZABX8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T4G2ZABX8

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES16T4G2 Data Sheet
The following tables list the functions of the pins provided on the PES16T4G2. Some of the functions listed may be multiplexed onto the same pin.
Note: In the PES16T4G2, the three downstream ports are labeled port 2, port 4, and port 6.
MSMBADDR[4:1]
PEREFCLKP[0]
PEREFCLKN[0]
PE0RN[3:0]
PE2RN[3:0]
PE4RN[3:0]
PE6RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE4RP[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE6RP[3:0]
PE6TP[3:0]
PE6TN[3:0]
MSMBCLK
MSMBDAT
REFCLKM
Signal
Signal
Type
Type
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Table 3 SMBus Interface Pins (Part 1 of 2)
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 PCI Express Interface Pins
4 of 31
Name/Description
Name/Description
September 13, 2010