IDT89HPES16T4ZHBCG IDT, Integrated Device Technology Inc, IDT89HPES16T4ZHBCG Datasheet - Page 7

• Manufacturer Part Number: IDT89HPES16T4ZHBCG
• Description: IC PCI SW 16LANE 4PORT 484-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4ZHBCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES16T4ZHBCG

IDT 89HPES16T4 Data Sheet
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
V
Signal
Signal
V
DD
V
V
V
DD
DD
TT
V
DD
CORE
SS
APE
PE
PE
IO
Type
Type
O
I
I
I
I
I
I
I
I
I
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Core V
I/O V
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
PCI Express Termination Power.
Ground.
Table 7 Power and Ground Pins
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
DD
DD
. LVTTL I/O buffer power supply.
. Power supply for core logic.
Table 6 Test Pins
7 of 31
Name/Description
Name/Description
March 25, 2008