IDT89HPES6T6G2ZBAL IDT, Integrated Device Technology Inc, IDT89HPES6T6G2ZBAL Datasheet - Page 6

• Manufacturer Part Number: IDT89HPES6T6G2ZBAL
• Description: IC PCI SW 6LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES6T6G2ZBAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES6T6G2ZBAL

IDT 89HPES6T6G2 Data Sheet
JTAG_TRST_N
V
REFRES0
REFRES1
REFRES2
REFRES3
REFRES4
REFRES5
V
V
Signal
Signal
V
DD
V
DD
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
Table 6 Power, Ground, and SerDes Resistor Pins
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is rec-
ommended to meet the JTAG specification in cases where the tester can
access this signal. However, for systems running in functional mode, one of
the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Port 1 External Reference Resistor. Provides a reference for the Port 1
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Port 3 External Reference Resistor. Provides a reference for the Port 3
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Port 5 External Reference Resistor. Provides a reference for the Port 5
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor
should be connected from this pin to ground.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
DD.
Table 5 Test Pins (Part 2 of 2)
DD.
LVTTL I/O buffer power supply.
Power supply for core logic.
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Name/Description
Name/Description
March 6, 2009