IDT89HPES4T4G2ZCAL IDT, Integrated Device Technology Inc, IDT89HPES4T4G2ZCAL Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT89HPES4T4G2ZCAL
Manufacturer Part Number
IDT89HPES4T4G2ZCAL
Description
IC PCI SW 4LANE 4PORT 324-FCBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT89HPES4T4G2ZCAL8.pdf
(29 pages)
Specifications of IDT89HPES4T4G2ZCAL
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89HPES4T4G2ZCAL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT89HPES4T4G2ZCAL
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES4T4G2ZCAL8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES4T4G2ZCALG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES4T4G2ZCALG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Hot-Plug Interface
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES4T4G2 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES4T4G2. In response to an I/O expander interrupt, the PES4T4G2 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
may be configured independently as an input or output through software control. Most GPIO pins are shared with other on-chip functions. These alter-
nate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
IDT 89HPES4T4G2 Data Sheet
The PES4T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4G2
The PES4T4G2 provides 7 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
PES4T4G2
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
...
Devices
SMBus
Other
3 of 29
(b) Split Configuration and Management Buses
PES4T4G2
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
September 13, 2010