LTC3731CUH Linear Technology, LTC3731CUH Datasheet - Page 24

• Manufacturer Part Number: LTC3731CUH
• Description: IC SW REG CTRLR SYNC BUCK 32QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3731CUH

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 ~ 6 V
• Frequency - Switching: 225kHz ~ 680kHz
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Power - Output: -

APPLICATIO S I FOR ATIO
LTC3731
1) Are the signal and power ground paths isolated? Keep the
2) Does the IC IN
3) Are the SENSE
24
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC
signal ground pin should be used to hook up all control
circuitry on one side of the IC, routing the copper through
SGND, under the IC covering the “shadow” of the pack-
age, connecting to the PGND pin and then continuing on
to the (–) plates of C
capacitor should be placed immediately adjacent to the
IC between the V
tor of the X7R or X5R type is small enough to fit very close
to the IC to minimize the ill effects of the large current
pulses drawn to drive the bottom MOSFETs. An addi-
tional 5µF to 10µF of ceramic, tantalum or other very low
ESR capacitance is recommended in order to keep the
internal IC supply quiet. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of
the Schottky diodes and (–) plates of C
have as short lead lengths as possible.
A 30pF to 300pF feedforward capacitor between the
IN
possible to the IC.
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE
SENSE
to the pins of the IC. Connect the SENSE
pins to the pads of the sense resistor as illustrated in
Figure 12.
+
and EAIN pins should be placed as close as
–
for each channel should be as close as possible
Figure 12. Kelvin Sensing R
LTC3731
SENSE
SENSE
+
–
CC
pin connect to the (+) plates of C
U
and SENSE
+
–
pin and PGND. A 1µF ceramic capaci-
IN
U
and C
1000pF
OUTPUT CAPACITOR
+
INDUCTOR
OUT
printed circuit traces for
W
. The V
SENSE
RESISTOR
3731 F12b
SENSE
IN
, which should
CC
–
and SENSE
decoupling
U
+
OUT
and
?
+
4) Do the (+) plates of C
5) Keep the switching nodes, SWITCH, BOOST and TG
6) Use a low impedance source such as a logic gate to
7) The 47pF to 330pF ceramic capacitor between the I
Figure 11 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec-
tric and magnetic fields will radiate from these “loops”
just as radio stations transmit signals. The output capaci-
tor ground should return to the negative terminal of the
input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regu-
lator. The ground terminations of the synchronous
MOSFETs and Schottky diodes should return to the
bottom plate(s) of the input capacitor(s) with a short
isolated PC trace since very high switched currents are
present. A separate isolated path from the bottom plate(s)
of the input and output capacitor(s) should be used to tie
in the IC power ground pin (PGND). This technique keeps
inherent signals generated by high current pulses tak-
ing alternate current paths that have finite impedances
during the total period of the switching regulator. Exter-
nal OPTI-LOOP compensation allows overcompensation
for PC layouts which are not optimized but this is not the
recommended design procedure.
topside MOSFETs as closely as possible? This capaci-
tor provides the pulsed current to the MOSFETs.
away from sensitive small-signal nodes (SENSE
SENSE
and TG printed circuit traces should be routed away
and separated from the IC and especially the “quiet”
side of the IC. Separate the high dv/dt traces from
sensitive small-signal nodes with ground traces or
ground planes.
drive the PLLIN pin and keep the lead as short as
possible.
pin and signal ground should be placed as close as
possible to the IC.
–
, IN
+
, IN
–
, EAIN). Ideally the SWITCH, BOOST
PWR
connect to the drains of the
3731fb
TH
+
,