ADP1829ACPZ-R7 Analog Devices Inc, ADP1829ACPZ-R7 Datasheet - Page 8

• Manufacturer Part Number: ADP1829ACPZ-R7
• Description: IC BUCK SYNC ADJ 100uA 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Step-Down (Buck)r

Specifications of ADP1829ACPZ-R7

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 15 V
• Current - Output: 100µA
• Frequency - Switching: 300kHz, 600kHz
• Voltage - Input: 3 ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Power - Output: 1W
• Primary Input Voltage: 20V
• No. Of Outputs: 2
• Output Voltage: 17V
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 1MHz
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADP1829-EVALZ - BOARD EVALUATION ADP1829
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADP1829ACPZ-R7TR

ADP1829
Pin No.
23
24
25
26
27
28
29
30
31
32
Mnemonic
BST1
POK1
EN1
EN2
LDOSD
IN
VREG
SS1
TRK1
COMP1
EPAD
Description
Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up
resistor from POK1 to VREG.
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG.
Otherwise, connect LDOSD to GND or leave it open, as it has an internal 100 kΩ pull-down resistor.
Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1829 from the LDO.
For input voltages between 3.0 V and 5.5 V, tie IN to VREG and PV.
Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG.
Bypass VREG to ground plane with 1 μF ceramic capacitor.
Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage.
If the tracking function is not used, connect TRK1 to VREG.
Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
The exposed pad must be connected to AGND.
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