L6712ADTR STMicroelectronics, L6712ADTR Datasheet - Page 22

• Manufacturer Part Number: L6712ADTR
• Description: IC CTRLR DC/DC 2PH SYNC 28SOIC
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6712ADTR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.9 ~ 3.3 V
• Current - Output: 2A
• Frequency - Switching: 150kHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Power - Output: 2W
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-4218-2

L6712A L6712
Figure 18. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right).
The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB
axes with a constant -20dB/dec slope with the desired crossover frequency ω
ZF(s), the transfer function has one zero and two poles. Both the poles are fixed once the output filter is
designed and the zero is fixed by ESR and the Droop resistance.
To obtain the desired shape an R
at ω
while placing the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is
assured (See Figure 18). In fact, considering the usual value for the output filter, the LC resonance results
to be at frequency lower than the above reported zero.Compensation network can be simply designed
placing ω
3.12.3Voltage Mode (VM) Control Loop (DROOP = SGND)
Disconnecting the DROOP pin from the Control Loop, the system topology becomes a Voltage Mode. The
simplest way to compensate this loop still keeping the same compensation network consists in placing the
RF-CF zero in correspondence with the L-C filter resonance.
The loop gain becomes now:
3.13 LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important
things to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the performance of the
control loops.
22/29
V
COMP
PWM
F
=1/R
Z
COMP
F
= ω
Z
C
F
d•V
F
C
LC
F
is then introduced together with an integrator. This integrator minimizes the static error
R
IN
I
and imposing the cross-over frequency ω
F
DROOP
R
L/2
=
F
Cout
ESR
FB
R
---------------------------------- - 5
VID
G
FB
LOOP
DROOP
⋅
V
R
V
∆V
IN
FB
OUT
Rout
s ( )
OSC
F
-C
=
⋅
RA_Gain
F
-- - ω
4
–
------------------ -
∆
series network is considered for the Z
⋅
V
V
OSC
T
IN
⋅
--------------------------------------------------------- -
2
⋅
⋅
⎛
⎝
Z
-------------- -
R
------------------------ -
RA_Gain
R
F
K
FB
s ( )
DROOP
K
=
dB
⋅
⎡
⎢
⎣
4
5
L
----------------------------------- - RA_Gain
Z
⋅
P
∆V
s ( )
V
+
T
Z
IN
OSC
as desired obtaining:
ESR
P
+
s ( )
⋅
Z
R
1
L
FB
⎞
⎠
ω
s ( )
⎤
⎥
⎦
LC
dB
⋅
G
LOOP
ω
Z
C
F
F
(s) implementation. A zero
T
=
. Neglecting the effect of
------------------- -
Co
R
F
⋅
L
-- -
2
ω
Z
T
F
(s)
ω