L6712 STMicroelectronics, L6712 Datasheet
L6712
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L6712 Summary of contents
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... Over / Under voltage.An internal crowbar is provided turning on the low side mosfet if Over-voltage is detected. Output current is limited working in Constant Cur- rent mode: when Under Voltage is detected, the device resets, restarting operation. L6712 L6712A SO28 VFQFPN-36 (6x6x1.0mm) Tube Tape & Reel L6712DTR, L6712ADTR L6712QTR, L6712AQTR Rev. 3 1/29 ...
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... L6712A L6712 Figure 2. Block Diagram BAND-GAP BAND-GAP REFERENCE REFERENCE PGOOD PGOOD LOGIC AND LOGIC AND VID2 VID2 PROTECTIONS PROTECTIONS VID1 VID1 DAC DAC VID0 VID0 DIGITAL DIGITAL SOFT-START SOFT-START V V REF_IN/OUT REF_IN/OUT FBG FBG FBR FBR REMOTE REMOTE AMPLIFIER AMPLIFIER VSEN ...
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... PGND; VCC=BOOTx=12V VCC Rising; VCCDR=5V VCC Falling; VCCDR=5V VCCDR Rising VCC=12V VCCDR Falling VCC=12V OSC = OPEN OSC = OPEN; Tj=0°C to 125°C I =5mA SINK L6712, OSC = OPEN: I DROOP OSC = OPEN; I =70µA DROOP L6712A, OSC = OPEN OVP Active L6712A L6712 ...
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... L6712A L6712 Table 4. Electrical Characteristcs (continued 12V±10 0°C to 70°C unless otherwise specified Symbol Parameter REFERENCE AND DAC Output Voltage Accuracy VIDx See Table 5, VID ≠ “11x“ (1) V OUT REF_IN/OUT Reference Accuracy Current Capability Load Regulation V / REF_IN/ ...
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... All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is connected to the error amplifier output and is used to compensate the control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the control feedback loop. L6712A L6712 Min. Typ. Max. 108 112 ...
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... L6712A L6712 Table 6. Pin Function (continued) N. (*) Name SO VFQFPN 10 9 DROOP 11 11 REF_IN / OUT 12 12 VSEN 13 13 ISEN1 14 14 PGNDS1 15 15 PGNDS2 16 16 ISEN2 17 18 OSC/INH FAULT 18 20 FBG 19 21 FBR 6/29 A current proportional to the sum of the current sensed in both channel is sourced from this pin (50µA at full load, 70µA at the Constant Current threshold). ...
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... VCC BOOT1 BOOT2 UGATE1 UGATE2 PHASE1 PHASE2 LGATE1 LGATE2 ISEN1 ISEN2 Rg L6712 PGNDS1 PGNDS2 L6712A Rg PGND VID2 PGOOD VID1 COMP VID0 DROOP OSC / INH FB SGND VSEN FBR FBG L6712A L6712 Description C IN HS2 L2 C OUT LS2 LOAD PGOOD 7/29 ...
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... L6712A L6712 3 Device Description The device is an integrated circuit realized in BCD technology. It provides complete control logic and pro- tections for a high performance dual-phase step-down converter optimized for high current DC/DC appli- cations designed to drive N-Channel Mosfets in a two-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses ...
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... The voltage identification (VID) pin configuration or the external reference provided also sets the power- good thresholds (PGOOD) and the Over/Under voltage protection (OVP/UVP) thresholds. 800 700 600 500 400 300 200 100 0 100 125 150 voltage reference (i.e. the set-point of the error amplifier). PROG L6712A L6712 150 250 350 450 550 Frequency (kHz) 650 9/29 ...
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... L6712A L6712 Figure 6. Reference Management BAND-GAP REFERENCE (1.235V) VID3 VID2 VID1 REF_IN/OUT The output regulated voltage accuracy can be extracted from the following relationships (worst case con- dition OUT_TOT_ACC [ ] EXT_REF_Accuracy[%] OUT_TOT_ACC EXT_REF_Accuracy[%] = where V and V are the offsets related to the Error Amplifier and the Remote Amplifier respec- ...
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... PGNDSx pins toward the reading points. The differential current reading rejects noise and allows to place sensing element in different locations without affecting the measurement's accuracy. The current reading ) in series to the LS mosfet and internally converted into a current. The L6712A L6712 CH3 = LGATE1; CH4 = LGATE2 dsON ...
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... L6712A L6712 circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet R imum rating overcome on ISENx pin) ...
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... I ■ L6712 - Dynamic Maximum Duty Cycle Limitation The maximum duty cycle is limited as a function of the measured current and, since the oscillator frequen fixed once programmed, imply a maximum on-time limitation as follow (where T is the switching pe- ...
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... L6712A L6712 usual way until another OCP event is detected. This means that the average current delivered can slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the I bottom ...
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... L6712A - Fixed Maximum Duty Cycle Limitation The maximum duty cycle is fixed and constant with the delivered current. The device works in constant current operation once the OCP threshold has overcome. Refer to the above Constant Current section in ...
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... L6712A L6712 3.6 INTEGRATED DROOP FUNCTION (Optional) Droop function realizes dependence between the regulated voltage and the delivered current (Load Reg- ulation). In this way, a part of the drop due to the output capacitor ESR in the load transient is recovered. As shown in Figure 12, the ESR drop is present in any case, but using the droop function the total devia- tion of the output voltage is minimized ...
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... Forcing the OSC/INH pin to a voltage lower than 0.5V (Typ.) disables the device: all the power mos- fets and protections are turned off until the condition is removed. Figure 14. Soft Start CCDR V LGATEx V OUT PGOOD 2048 Clock Cycles Timing Diagram Turn ON threshold CH1=PGOOD; CH2=VOUT; CH3=REF_OUT L6712A L6712 Acquisition: 17/29 ...
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... L6712A L6712 3.9 INPUT CAPACITOR The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as reported in Figure 15. Considering the two-phase topology, the input RMS current is highly reduced comparing with a single-phase operation. It can be observed that the input RMS value is one half of the single-phase equivalent input current in the worst case condition that happens for D=0 ...
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... The inductance L V – OUT OUT ⋅ ----------------------------- - -------------- - ∆I ⋅ the input voltage and ∆I ⋅ ----------------------------- - t = removal V – OUT L6712A L6712 – OUT IN is the output voltage. OUT L ∆I ⋅ -------------- - = V OUT 19/29 ...
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... L6712A L6712 Figure 16. Main Control Loop Diagram + + D03IN1518 3.12.1Current Sharing (CS) Control Loop Active current sharing is implemented using the information from Trans conductance differential amplifier. A current reference equal to the average of the read current (I read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See Figure 17) ...
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... L ⋅ ⋅ ⋅ -------------- - ------------------------------------------------------------------------------------------------------------------------------------------ - RA_Gain ⋅ ⋅ ⋅ --------------- ⋅ L6712A L6712 /2). MAX DROOP ⋅ RA_Gain ⎛ ⎞ ⋅ ----------- - ⎝ ⎠ the oscillator ramp amplitude OSC ⋅ ⎛ ⎞ RA_Gain ⋅ ...
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... L6712A L6712 Figure 18. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right). I DROOP Z F DROOP COMP FB COMP VID L/2 V OUT PWM d•V IN Cout ESR The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ω ...
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... High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if BOOTx PHASEx L C OUT VCC LOAD SGND b. PCB small signal components placement L6712A L6712 BOOTx OUT ...
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... L6712A L6712 implemented the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested). Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the sys- tem efficiency ...
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... Figure 21. PCB layout connections for sense nets. NOT CORRECT VIA to GND plane Wrong (left) and correct (right) connections for the current reading sensing nets. as current sense element, the ISENx pin is practically dsON To PHASE connection L6712A L6712 . dsON CORRECT To LS Drain and Source To HS Gate and Source ...
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... L6712A L6712 4 Package informations Figure 22. SO-28 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. MAX. A 2.65 a1 0.1 0.3 b 0.35 0.49 b1 0.23 0.32 C 0.5 c1 45° (typ.) D 17.7 18 10.65 e 1.27 e3 16.51 F 7.4 7.6 L 0.4 1.27 8 ° (max.) S 26/29 inch MIN. TYP. MAX. 0.104 0.004 0.012 0.014 0.019 0.009 0.013 0.020 0.697 0.713 0.394 0.419 ...
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... VFQFPN-36 (6x6x1.0mm) 0.014 0.022 0.029 Very Fine Quad Flat Package No lead 0.003 L6712A L6712 OUTLINE AND MECHANICAL DATA 7185332 F 27/29 ...
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... L6712A L6712 5 Revision History Table 7. Revision History Date Revision March 2004 June 2005 28/29 2 First Issue in EDOCS. 3 Changed look and feel. Inserted “Boot Capacitor Extra Charge” paragraph to page 27. Description of Changes ...
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