MAX1977EEI+ Maxim Integrated Products, MAX1977EEI+ Datasheet - Page 30

• Manufacturer Part Number: MAX1977EEI+
• Description: IC CNTRLR PS QUAD HI EFF 28QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1977EEI+

• Applications: Controller, Notebook Computers
• Voltage - Input: 4.5 ~ 24 V
• Number Of Outputs: 4
• Voltage - Output: 3.3V, 5V, 2 ~ 5.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Output Voltage: 3.3 V, 2 V to 5.5 V
• Input Voltage: 6 V to 24 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Case: SSOP
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Efficiency, Quad Output, Main Power-
Supply Controllers for Notebook Computers
Figure 13. PC Board Layout Example
• Use a star ground connection on the power plane to
• Keep the high-current paths short, especially at the
• Keep the power traces and load connections short.
• CS_ (MAX1777/MAX1977) / LX_ (MAX1999) and GND
• When trade-offs in trace lengths must be made, it is
30
PGND5). Avoid the introduction of AC currents into
the PGND3 and PGND5 ground planes. Run the
power plane ground currents on the top side only, if
possible.
minimize the crosstalk between OUT3 and OUT5.
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable effi-
ciency penalty.
connections to the synchronous rectifiers for current
limiting must be made using Kelvin sense connec-
tions to guarantee the current-limit accuracy. With 8-
pin SO MOSFETs, this is best done by routing power
to the MOSFETs from outside using the top copper
layer, while connecting CS_/LX_ traces inside (under-
neath) the MOSFETs.
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
______________________________________________________________________________________
ANALOG GROUND
PLANE ON INNER LAYER
USE AGND PLANE TO:
- BYPASS V
- TERMINATE EXTERNAL FB
- TERMINATE R
- PIN-STRAP CONTROL
INPUTS
DIVIDER (IF USED)
(IF USED)
CC
CONNECT PGND TO AGND
BENEATH THE CONTROLLER AT
ONE POINT ONLY AS SHOWN.
AND REF
ILIM
AGND
USE PGND PLANE TO:
- BYPASS LDO_
- CONNECT PGND TO THE TOPSIDE STAR GROUND
AND ANALOG GROUND
VIA BETWEEN POWER
VIAS TO GROUND
PGND
NOTE: EXAMPLE SHOWN IS FOR DUAL N-CHANNEL MOSFET.
VIA TO OUT5
VIA TO LX5
OUT5
L1
C3
• Ensure that the OUT_ connection to C
• Route high-speed switching nodes (BST_, DH_, LX_,
• Make all pin-strap control input connections (SKIP,
1) Place the power components first with ground ter-
2) Mount the controller IC adjacent to the synchronous
3) Group the gate-drive component (BST_ diode and
allow distance between the inductor and the syn-
chronous rectifier or between the inductor and the
output filter capacitor.
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the
OUT_ connector node and the output filter capacitor
(see the Stability Considerations section).
and DL_) away from sensitive analog areas (REF,
ILIM_, and FB_). Use PGND3 and PGND5 as an EMI
shield to keep radiated switching noise away from the
IC’s feedback divider and analog bypass capacitors.
ILIM_, etc.) to GND or V
N4
minals adjacent (N2/N4 source, C
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
rectifier MOSFETs, preferably on the back side in
order to keep DH_, GND, and the DL_ gate drive
lines short and wide. The DL_ gate trace must be
short and wide measuring 50mils to 100mils wide if
the MOSFET is 1in from the controller device.
capacitor, V+ bypass capacitor) together near the
controller device.
N3
GROUND
C1
V+
C2
N1
N2
VIA TO LX3
VIA TO PGND
C4
CC
OUT3
L2
of the device.
Layout Procedure
VIA TO OUT3
OUT_
IN_
, C
is short and
OUT_
, D1