ISL6312ACRZ Intersil, ISL6312ACRZ Datasheet
ISL6312ACRZ
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ISL6312ACRZ Summary of contents
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... Ordering Information PART NUMBER PART (Note) MARKING ISL6312ACRZ* ISL6312 ACRZ 7x7 QFN L48.7x7 ISL6312AIRZ* ISL6312 AIRZ - 7x7 QFN L48.7x7 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Pinout VID4 VID3 VID2 VID1 VID0 VRSEL DRSEL OVPSEL SS VCC REF OFS ISL6312A Integrated Driver Block Diagram DRSEL PWM SOFT-START AND FAULT LOGIC 2 ISL6312A ISL6312A ISL6312A (48 LD QFN) TOP VIEW ...
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Block Diagram OPEN SENSE LINE PREVENTION VSEN x1 RGND VDIFF UNDERVOLTAGE DETECTION LOGIC OVERVOLTAGE DETECTION LOGIC OVPSEL MODE / DAC VRSEL SELECT VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 I_TRIP VID1 VID0 REF E/A FB COMP OFS OFFSET ...
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Typical Application - ISL6312A (4-Phase) FB VDIFF COMP VSEN RGND +5V VCC OFS FS REF SS OVPSEL ISL6312A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN IOUT DRSEL GND 4 ISL6312A ISL6312A +12V BOOT1 UGATE1 PHASE1 ...
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Typical Application - ISL6312A with NTC Thermal Compensation (4-Phase) FB VDIFF COMP VSEN RGND +5V VCC OFS FS REF SS OVPSEL VID7 ISL6312A VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD +12V EN IOUT DRSEL GND 5 ISL6312A ISL6312A ...
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... BOOT - PHASE - 0. 0.3V Recommended Operating Conditions BOOT + 0.3V BOOT VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL6312ACRZ 0°C to +70°C Ambient Temperature (ISL6312AIRZ .-40°C to +85°C TEST CONDITIONS high VCC high PVCC1_2 high ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER DAC Input Low Voltage (AMD) DAC Input High Voltage (AMD) PIN-ADJUSTABLE OFFSET OFS Sink Current Accuracy (Negative Offset) OFS Source Current Accuracy (Positive Offset) ERROR AMPLIFIER DC Gain Gain-Bandwidth Product ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-On Non-Overlap LGATE Turn-On Non-Overlap GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive ...
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Functional Pin Description VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1μF ceramic capacitor. PVCC1_2 and PVCC3 These pins are the power supply pins for ...
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... PWM4 Pulse-width modulation output. Connect this pin to the PWM input pin of an Intersil driver IC if 4-phase operation is desired. EN_PH4 This pin has two functions. First, a resistor divider connected to this pin will provide a POR power up synch between the on-chip and external driver. The resistor divider should be designed so that when the POR-trip point of the external driver is reached the voltage on this pin should be 1 ...
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... PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor between the FS pin and ground. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the 11 ...
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... Intersil’s patented current- balance method is illustrated in Figure 3, with error correction for Channel 1 represented. In the figure, the cycle average current compared with the Channel 1 AVG sample create an error signal I ...
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L ⎛ ⎞ 1 ------------- + ⎝ ⎠ DCR ⋅ ⋅ ------------------------------------------------------- - K DCR ⋅ ) ⎛ ⎞ ⋅ ⋅ ⎜ s ----------------------- - C ...
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TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 VID5 ...
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TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION CODES (Continued) VID4 VID3 VID2 VID1 VID0 ...
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TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ...
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... DAC) and offset errors in the OFS current source, 1 0.8250 remote-sense and error amplifiers. Intersil specifies the 0 0.8000 guaranteed tolerance of the ISL6312A to include the combined tolerances of each of these elements. 1 0.7750 0 0 ...
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Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, V connected to the inverting input of the error ...
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OFS OFS FB + VDIFF 1:1 CURRENT MIRROR I OFS VCC R OFS OFS ISL6312A FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING OFS OFS - VDIFF VCC 1:1 I ...
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User Selectable Adaptive Deadtime Control Techniques The ISL6312A integrated drivers incorporate two different adaptive deadtime control techniques, which the user can choose between. Both of these control techniques help to minimize deadtime, resulting in high efficiency from the reduced freewheeling ...
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Initialization Prior to initialization, proper conditions must exist on the EN, VCC, PVCC and the VID pins. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, the controller asserts ...
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VOUT, 500mV/DIV TD1 TD2 TD3 TD4 EN_VTT PGOOD 500µs/DIV FIGURE 11. SOFT-START WAVEFORMS TD1 is a fixed delay with the typical value as 1.40ms. TD3 is determined by the fixed 85µs plus the time to obtain valid VID voltage. If ...
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Fault Monitoring and Protection The ISL6312A actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system ...
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For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor. In the event that during normal operation the PVCC or VCC voltage falls back below ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...
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The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 26, 27, 28 and 29. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs ...
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Inductor DCR Current Sensing Component Selection The ISL6312A senses each individual channel’s inductor current by detecting the voltage across the output inductor DCR of that channel (As described in the “Continuous Current Sampling” on page 12). As Figure 18 illustrates, ...
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FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR Loadline Regulation Resistor For loadline regulation a copy of the internal average sense current flows out of the FB pin across the loadline regulation resistor, labeled R in Figure 6. This resistor’s ...
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Case π ⋅ ⋅ ⋅ π f ⋅ ⋅ ⋅ ⋅ ------------------------------------------------------- - ⋅ 0.66 V ⋅ 0. ...
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Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. ...
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L(P- 0.5 I L(P- 0.75 I L(P- 0.2 0.4 0.6 DUTY CYCLE (V IN/ FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER Layout Considerations MOSFETs ...
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VDIFF COMP VSEN RGND +5V VCC (CF1) R OFS OFS FS REF REF OVPSEL ISL6312A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 4/10 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 35 ...