ISL6312ACRZ Intersil, ISL6312ACRZ Datasheet - Page 30

• Manufacturer Part Number: ISL6312ACRZ
• Description: IC CTRLR PWM 4PHASE BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6312ACRZ

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 5 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Case 3:
In Equation 44, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V
peak-to-peak sawtooth signal amplitude as described in the
“Electrical Specifications” on page 6.
Once selected, the compensation values in Equation 44
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equation 44 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 20). Keep
a position available for C
high frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
Case 2:
Case 1:
C
will not need adjustment. Keep the value of C
C
while observing the transient performance on an
R
C
------------------------------- -
2 π
C
C
⋅
R
C
------------------------------- -
2 π
f
R
C
⋅
C
C
=
=
0
⋅
1
C
C
>
=
=
R
-------------------------------------------------------------------------------------
(
⋅
L C
2 π
1
=
=
------------------------------------ -
2 π C ESR
FB
R
--------------------------------------------------- -
2 π V
⋅
⋅
L C
⋅
R
----------------------------------------------------------------
2 π V
FB
⋅
⋅
⋅
)
0.66 V
FB
⋅
≤
V
---------------------------------------------------------------- -
2
⋅
2
2
⋅
⋅
0.66 V
f
PP
⋅
, is sometimes needed to bypass
1
, and be prepared to install a
>
0
2 π f
------------------------------------------------------- -
⋅
⋅
f
⋅
PP
<
0
f
⋅
-------------------------------------------- -
0.66 V
⋅
2 π f
2
0
⋅
0.66 V
30
PP
------------------------------------ -
2 π C ESR
(
⋅
⋅
⋅
2 π
0.66 V
IN
⋅
⋅
⋅
V
0.66 V
R
⋅
⋅
0
IN
PP
⋅
⋅
⋅
R
FB
⋅
⋅
⋅
ESR
)
0
FB
V
⋅
2
1
IN
IN
⋅
⋅
⋅
⋅
pp
⋅
R
⋅
V
f
⋅
0
IN
⋅
C
f
FB
IN
pp
f
0
⋅
ESR
⋅
0
2
. Slowly increase the
PP
⋅
⋅
⋅
⋅
L C
C
L C
L
⋅
L
is the
L C
⋅
⋅
C
from
(EQ. 44)
ISL6312A
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount:
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 47 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 48
ΔV ESL
L
≥
MAX
≈
ESR
. This places an upper limit on inductance.
⋅
⋅
PP(MAX)
⎛
⎝
------------------------------------------------------------------- -
---- -
dt
di
V
IN
f
+
S
ESR ΔI
–
⋅
MAX
V
N V
IN
, determines the lower limit on the
⋅
⋅
⋅
.
OUT
V
PP MAX
C,PP
⎞ V
⎠
(
⋅
OUT
(ESR). Thus, once the output
)
February 1, 2011
MAX
(EQ. 45)
(EQ. 46)
FN9290.5
.