ISL6313B Intersil Corporation, ISL6313B Datasheet
ISL6313B
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ISL6313B Summary of contents
Page 1
... Integrated into the ISL6313B are user programmable current sense resistors, which require only a single external resistor to set their values. No external current sense resistors are required. Another unique feature of the ISL6313B is the addition of a dynamic VID compensation pin that allows optimizing compensation to be added for well controlled dynamic VID response ...
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... Pinout www.DataSheet4U.com PGOOD VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ISL6313B Integrated Driver Block Diagram PWM SOFT-START AND FAULT LOGIC 2 ISL6313B ISL6313B ISL6313B (36 LD TQFN) TOP VIEW GND SHOOT- ...
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... VID4 VID D/A VID3 VID2 VID1 VID0 + + ∑ RGND x2 DVC 2kΩ REF FB COMP OFFSET OFS x1 IOUT OCP V OCP 3 ISL6313B ISL6313B PGOOD SOFT-START AND FAULT LOGIC ADAPTIVE PHASE ALLIGNMENT CIRCUITRY CLOCK AND MODULATOR WAVEFORM GENERATOR OCP ∑ + I_TRIP - + ∑ - E/A FS I_AVG CHANNEL CURRENT BALANCE EN 0 ...
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... Typical Application - ISL6313B www.DataSheet4U.com FB DVC VSEN COMP APA +5V VCC OFS FS REF SS IOUT ISL6313B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PGOOD EN GND 4 ISL6313B ISL6313B RGND +5V VCC +12V RSET BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ISEN1+ +12V PVCC BOOT2 UGATE2 PHASE2 LGATE2 ...
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... Typical Application - ISL6313B with NTC Thermal Compensation www.DataSheet4U.com FB DVC VSEN COMP APA +5V VCC OFS FS REF SS IOUT ISL6313B VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PGOOD EN GND 5 ISL6313B ISL6313B RGND +5V VCC RSET +12V BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ISEN1+ +12V PVCC ...
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... BOOT - PHASE - 0. 0.3V BOOT Recommended Operating Conditions + 0.3V BOOT VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6313BCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6313BIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS ; EN = high VCC ; EN = high PVCC = 100kΩ (±0.1 100kΩ (±0.1%) T θ ...
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... R (ISL6313BCRZ) IOUT Current Sense Gain R (ISL6313BIRZ) OVERCURRENT PROTECTION Overcurrent Trip Level - Average Normal operation (ISL6313BCRZ) Channel Normal operation (ISL6313BIRZ) Dynamic VID change Overcurrent Trip Level - Individual Normal operation Channel Dynamic VID change IOUT Pin Overcurrent Trip Level PROTECTION Undervoltage Threshold VSEN falling ...
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... Lower Drive Sink Resistance V OVER-TEMPERATURE SHUTDOWN (Note 3) Thermal Shutdown Setpoint Thermal Recovery Setpoint Timing Diagram t PDHUGATE UGATE LGATE t FLGATE 8 ISL6313B ISL6313B TEST CONDITIONS V = 12V, 3nF load, 10% to RUGATE; PVCC V = 12V, 3nF load, 10% to RLGATE; PVCC V = 12V, 3nF load, 90% to FUGATE; PVCC ...
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... Connect this pin to the Ground sense pin or point of the microprocessor. 9 ISL6313B ISL6313B FB and COMP These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VSEN pins are tied together through external R-C networks to compensate the regulator ...
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... The ISL6313B controller helps simplify implementation by integrating vital functions and requiring minimal external components. The block diagram on page 3 provides a top level view of multi- phase power conversion using the ISL6313B controller. PWM1, 5V/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS Interleaving ...
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... APA,TRIP COMP FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION Adaptive Phase Alignment (APA) To further improve the transient response, the ISL6313B also implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the channels together at the same time during large current step transient events ...
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... APA TRIP APA Number of Active Channels The default number of active channels on the ISL6313B is two for 2-phase operation. If single-phase operation is desired the ISEN2- pin should be tied to the VCC pin. This will disable Channel 2, so only Channel 1 will fire. In single phase operation all of the Channel 2 pins should be left unconnected including the PHASE2, LGATE2, UGATE2, BOOT2, and ISEN2+ pins ...
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... R ISEN+ Output Voltage Setting RSET VCC The ISL6313B uses a digital to analog converter (DAC SET generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables the Intel VR11 mode of operation, each VID pin is pulled internal 1.2V voltage by a weak current source (40µ ...
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... ISL6313B TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1.56875 1.56250 1.55625 1.55000 ...
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... ISL6313B TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1.06875 1.06250 1.05625 1.05000 ...
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... ISL6313B TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION CODES VDAC VID4 1 1 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 ...
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... DAC) and offset errors in the OFS current source, 0 remote-sense and error amplifiers. Intersil specifies the 0.8000 guaranteed tolerance of the ISL6313B to include the 1 0.7750 combined tolerances of each of these elements. 0 0.7625 The output of the error amplifier ...
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... ISEN Output-Voltage Offset Programming The ISL6313B allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current ( flow into the OFS pin OFS and out of the FB pin, providing a negative offset ...
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... Modern microprocessors need to make changes to their core www.DataSheet4U.com voltage as part of normal operation. They direct the ISL6313B to do this by making changes to the VID inputs. The ISL6313B is required to monitor the DAC inputs and respond to on-the- fly VID changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption ...
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... Enable and Disable While in shutdown mode, the LGATE and UGATE signals 0.6 0.7 0.8 0.9 1.0 are held low to assure the MOSFETs remain off. The (V) following input conditions must be met, for both Intel and AMD modes of operation, before the ISL6313B is released Q GATE ≥ ------------------------------------- - ΔV BOOT_CAP ⋅ Q PVCC G1 ⋅ ...
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... The voltage on EN must be above 0.85V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6313B in shutdown until the voltage at EN rises above 0.85V. The enable comparator has 110mV of hysteresis to prevent bounce. ...
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... PGOOD 500µs/DIV FIGURE 14. SOFT-START WAVEFORMS Pre-Biased Soft-Start The ISL6313B also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. ...
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... Once an overvoltage condition ends the ISL6313B latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated. There is an OVP condition that exists that will not latch off the ISL6313B ...
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... FIGURE 17. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The ISL6313B has the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 140µA OCL reference current as shown in Figure 16 channel’ ...
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... See “Layout Considerations” on page 31 for thermal transfer improvement suggestions. When designing the ISL6313B into an application recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P the gate charge of MOSFETs and the integrated driver’ ...
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... G1 EXT2 ISL6313B Inductor DCR Current Sensing Component Selection D The ISL6313B senses each individual channel’s inductor C GD current by detecting the voltage across the output inductor DCR of that channel (As described in “Continuous Current C DS Sensing” on page 12). As Figure 20 illustrates, an R-C R GI1 ...
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... Figure 7. This resistor’s FB value sets the desired loadline required for the application. The desired loadline can be calculated by Equation 37 LL where V is the desired droop voltage at the full load DROOP current I FL. 27 ISL6313B . V DROOP R = ------------------------ - LL (EQ. 35) Based on the desired loadline, the loadline regulation resistor ...
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... R FB VSEN FIGURE 22. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6313B CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution ...
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... Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). 29 ISL6313B , but it can be At the beginning of the load transient, the output capacitors 0 can supply all of the transient current. The output voltage will ...
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... MOSFETs which is related to duty cycle and the number of active phases. For a two-phase design, use Figure 25 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I 30 ISL6313B 0.3 ⎞ (EQ. 46 – ...
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... Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6313B to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 ISL6313B VSEN RGND +5V VCC ...
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... LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 08/08 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 4.15) Exp. Dap 4.15) Exp. Dap 4.00) TYPICAL RECOMMENDED LAND PATTERN 33 ISL6313B 4. 36X 0.55 ± 0.10 BOTTOM VIEW Max 0.80 ( 32x 0.50) SIDE VIEW REF C (36X .25 MIN MAX. ...