LTC3831EGN-1 Linear Technology, LTC3831EGN-1 Datasheet - Page 6

• Manufacturer Part Number: LTC3831EGN-1
• Description: IC CTRLR SW REG SYNC DDR 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC3831EGN-1

• Applications: Controller, DDR
• Voltage - Input: 3 ~ 8 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PI FU CTIO S
LTC3831-1
TG ( Pin 1): Top Driver Output. Connect this pin to the gate
of the upper N-channel MOSFET, Q1. This output swings
from PGND to PV
shutdown mode.
PV
to a potential of at least V
operation, PV
2V when TG is high. This allows the use of an external
charge pump to power PV
PGND (Pin 3): Power Ground. Both drivers return to this
pin. Connect this pin to a low impedance ground in close
proximity to the source of Q2. Refer to the Layout Consid-
eration section for more details on PCB layout techniques.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3831-1.
R
resistor divider that generate the internal ratiometric ref-
erence for the error amplifier. The reference voltage is set
at 0.5 • (V
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external resis-
TYPICAL PERFOR A CE CHARACTERISTICS
6
–
, R
CC1
U
10
80
70
60
50
40
30
20
0
0
PV
vs Gate Capacitance
+
T
(Pin 2): Power Supply Input for TG. Connect this pin
(Pins 5, 7): These two pins connect to the internal
A
CC
GATE CAPACITANCE AT TG AND BG (nF)
= 25 C
1
U
R
Supply Current
2
+ – V
CC1
3
R
CC1
4
must also be higher than V
–).
PV
U
5
CC1,2
PV
. It remains low if BG is high or during
CC1,2
6
= 12V
= 5V
7
CC1
IN
W
8
.
+ V
3831 G20
9
U
GS(ON)(Q1)
10
200
180
160
140
120
100
. For normal
CC
80
60
40
20
0
0
TG Rise/Fall Time
vs Gate Capacitance
by at least
T
A
GATE CAPACITANCE AT TG AND BG (nF)
1
= 25 C
2
t
r
AT PV
t
f
AT PV
3
CC1,2
4
CC1,2
t
tor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831-1
can operate with a minimum V
V
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100 s puts the LTC3831-1 into
shutdown mode. In shutdown, TG and BG go low, all
internal circuits are disabled and the quiescent current
drops to 10 A max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also double as
an external clock input to synchronize the internal oscilla-
tor with an external clock.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, C
LTC3831-1 goes into current limit, C
reduce the duty cycle. C
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10): External Compensation. This pin inter-
nally connects to the output of the error amplifier and input
of the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
= 5V
r
5
AT PV
FB
= 5V
t
f
6
AT PV
of (V
CC1,2
7
CC1,2
= 12V
8
CC
= 12V
3831 G21
9
SS
– 2V).
, to implement a soft-start function. If the
10
50mV/DIV
2A/DIV
I
V
LOAD
OUT
SS
Transient Response
must be selected such that
FB
of 0.4V and maximum
SS
50 s/DIV
is discharged to
3831 G22.tif
38311f