LTC3831EGN-1 Linear Technology, LTC3831EGN-1 Datasheet - Page 12

• Manufacturer Part Number: LTC3831EGN-1
• Description: IC CTRLR SW REG SYNC DDR 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC3831EGN-1

• Applications: Controller, DDR
• Voltage - Input: 3 ~ 8 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC3831-1
APPLICATIO S I FOR ATIO
The charge pump capacitors for PV
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831-1
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the soft-
start capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low V
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831-1 overcomes this problem by sensing the
PV
above V
by clamping the COMP pin at 1.8V (Q
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
For applications using an external supply to power PV
this supply must also be higher than V
ensure normal operation.
12
CC1
CC
voltage when TG is high. If PV
CC
voltages and high switching frequencies, coupled
, the maximum TG duty cycle is reduced to 70%
U
U
10 F
2.2 F
W
CC1
V
CC
D
12V
1N5242
CC1
CC
Z
Figure 5. Triple Charge Pump Configuration
refresh when the
LTC3831-1
by at least 2V to
C
is less than 2V
PV
in the Block
1N5817
CC2
U
PV
1N5817
CC1
CC1
TG
BG
,
0.1 F
3.3V
V
Connecting the Ratiometric Reference Input
The LTC3831-1 derives its ratiometric reference, V
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R
The LTC3831-1 can operate with a minimum V
and maximum V
GND, this gives a V
If V
the V
In a typical DDR memory termination, as shown in the
typical application on the front page, R
V
The output voltage V
= 0.5 • V
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to V
pin. Figure 6 shows an application that generates a V
0.6 • V
CC
DDQ
1N5817
R
+
CC
, the supply voltage of the interface, and R
0.1 F
is higher than the permitted input voltage, increase
DDQ
voltage to raise the input range.
DDQ
1.5V
Q2
V
IN
.
Q1
.
L
O
FB
R
of (V
+
+
TT
input range of 0.8V to (2 • V
38311 F05
is connected to the FB pin, so V
C
OUT
CC
V
OUT
– 2V). With R
+
and R
+
is connected to
–
+
–
connected to
.
and R
FB
–
TT
CC
to GND.
of 0.4V
and FB
–
– 4V).
TT
pins
38311f
REF
TT
of
,