MC33023DWR2G ON Semiconductor, MC33023DWR2G Datasheet - Page 9

• Manufacturer Part Number: MC33023DWR2G
• Description: IC CTRLR PWM HS SGL ENDED 16SOIC
• Manufacturer: ON Semiconductor

Specifications of MC33023DWR2G

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 90%
• Voltage - Supply: 10 V ~ 30 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 1MHz
• Duty Cycle (max): 90 %
• Output Voltage: 5.05 V to 5.15 V
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 1000 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 105 C
• Fall Time: 30 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 30 ns
• Synchronous Pin: Yes
• Topology: Flyback, Forward
• Number Of Pwm Outputs: 1
• On/off Pin: Yes
• Adjustable Output: No
• Switching Freq: 1MHz
• Operating Supply Voltage (max): 30V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC33023DWR2GOS

frequency, single−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution
representative block diagram is shown in Figure 19.
Oscillator
selected for the timing components R
is set to a temperature compensated 3.0 V. By selecting the
value of R
for the timing capacitor C
continuously through C
be 10 times the charge current, which yields the maximum
duty cycle of 90%. C
1.0 V. During the discharge of C
internal blanking pulse that resets the PWM Latch and,
inhibits the outputs. The threshold voltage on the oscillator
comparator is trimmed to guarantee an oscillator accuracy
of 5.0% at 25°C.
increasing the charge current to C
This changes the charge to discharge ratio of C
internally to I
ratio will be:
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of C
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge C
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 28, 29 and 30 provide suggested
synchronization.
Error Amplifier
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a common mode voltage (V
5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Soft−Start Latch
external capacitor. The Soft−Start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
The MC33023 and MC34023 series are high speed, fixed
The oscillator frequency is programmed by the values
Additional dead time can be added by externally
A bidirectional clock pin is provided for synchronization
A fully compensated Error Amplifier is provided. It
Soft−Start is accomplished in conjunction with an
% Deadtime +
T
, the charge current is set through a current mirror
with
charge
minimal
/10 I
T
is charged to 2.8 V and discharged to
T
charge
. The discharge current is ratioed to
I additiona l ) I charge
T
. The new charge to discharge
external
. This charge current runs
T
10 (I charge )
, the oscillator generates an
CM
T
) input range of 1.5 V to
as shown in Figure 24.
T
and C
components.
T
OPERATING DESCRIPTION
T
. The R
which is set
http://onsemi.com
T
pin
A
T
T
.
.
9
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle. The time it takes for a
capacitor to reach full charge is given by:
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either V
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed and, the voltage at C
than 0.5 V.
PWM Comparator and Latch
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the error amplifier output voltage
minus 1.25 V, the PWM comparator will cause the PWM
latch to set, disabling the outputs. Once the PWM latch is set,
only a blanking pulse by the oscillator can reset it, thus
initiating the next cycle.
Current Limiting and Shutdown
shutdown operations. Two comparators are connected to the
input of this pin. The reference voltage for the current limit
comparator is not set internally. A pin is provided so the user
can set the voltage. When the voltage at the current limit
input pin exceeds the externally set voltage, the PWM latch
is set, disabling the output. In this way cycle−by−cycle
current limiting is accomplished. If a current limit resistor is
used in series with the power devices, the value of the
resistor is found by:
comparator is activated. This comparator sets a latch which,
in turn, causes the soft start capacitor to be discharged. In this
way a “hiccup” mode of recovery is possible in the case of
output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
A Soft−Start latch is incorporated to prevent erratic
A PWM circuit typically compares an error voltage with
A pin is provided to perform current limiting and
If the voltage at this pin exceeds 1.4 V, the second
R Sense +
t [ (4.5 • 10 5 ) C Soft-Start
I Limit Reference Voltage
I pk (switch)
CC
or V
ref
Soft−Start
. The second
is less