NCP1380CDR2G ON Semiconductor, NCP1380CDR2G Datasheet - Page 20

• Manufacturer Part Number: NCP1380CDR2G
• Description: IC PWM FLYBCK ISO CM 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1380CDR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 65kHz
• Voltage - Supply: 9.4 V ~ 28 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 65kHz
• Mounting Style: SMD/SMT
• Operating Supply Voltage: - 0.3 V to + 28 V
• Supply Current: +/- 30 mA
• Maximum Operating Temperature: + 125 C
• Fall Time: 25 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Quasi-Resonant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 37 shows the implementation of the fault timer.
R
counting: the timer count is incremented each 10 ms. When
the current comes back within safe limits, “Max Ip”
comparator becomes silent and the timer count down: the
timer count is decremented each 10 ms. In normal overload
conditions the timer reaches its completion when it has
counted up 8 times 10 ms.
completion, the circuit enter auto−recovery mode: the
circuit stops all operations and V
own consumption (I
circuit goes in startup mode and restart switching. (see
Figure 38) This ensures a low duty−cycle burst operation in
fault mode.
Laux
sense
When the current in the MOSFET is higher than V
On B and D version, when the timers reaches its
ZCD/OPP
, “Max Ip” comparator trips and the digital timer starts
R sen se
CS
LEB2
LEB1
CC1
V IL IM IT
). When V
FB/4
OPP
V CS(stop)
CC
Soft−start
CC
decreases via the circuit
SHORT−CIRCUIT OR OVERLOAD MODE
reaches V
Figure 37. Overload Detection Schematic
+
−
+
−
+
−
Soft −s t art end ?
t hen 1
else 0
CC(off)
PW Mr eset
IpFlag
SS en d
CsStop
http://onsemi.com
ILIM
, the
/
S
R
20
Q
Q
80 ms, the circuit goes in latch mode (Figure 39): the DRV
pulses stop and V
7.2 V typically. The circuit un−latches when the current
circulating in V
another comparator with a reduced LEB (t
threshold of 1.2 V is able to sense winding short−circuit and
immediately shut down the controller. Depending on the
version, this additional protection is either latched or
auto−recovery, according to the overload protection
behavior.
Down
Up
grand
reset
On A and C versions, when the timers finishes counting
In parallel to the cycle−by−cycle sensing of the CS pin,
TIMER
CsStop
Reset
DRV
A&C:
Latched
CC
CC
pin drops below I
R
S
is pulled down to V
latch
Q
Q
fau l t
Vd d
management
grand
reset
V
CC
CC(latch)
CC(latch)
VC C sto p
.
BCS
which is
) and a
VCC
au x