L5993D STMicroelectronics, L5993D Datasheet - Page 11

• Manufacturer Part Number: L5993D
• Description: IC PWM CONTROLLER 16 SOIC
• Manufacturer: STMicroelectronics

Specifications of L5993D

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 11 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 497-2387-5

start capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximately given by:
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is
(<150 A). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses
when a converter is lightly loaded.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 25,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is R
turn-off is R
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
T
hic
g
only.
4.5
I
SSC
1
I
SSD
1
C
extremely low
ss
7
g
+ R
g’,
at
Figure 25. Turn-on and turn-off speeds adjust-
Figure 26. Pull-Down of the output in UVLO
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
in fig.26) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from V
When the threshold is exceeded and the L5993
starts operating, V
26) and the circuit is disabled.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
V
REFOK
CONTROL
DRIVE &
L5993
D97IN767
V
CC
13V
8
ment
Rg’
PGND
CC
= 0V up to the start-up threshold.
REFOK
V
9
11
C
10
OUT
is pulled high (refer to fig.
Rg
D97IN538
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
10
12
OUT
SGND
L5993
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