W83792AG Nuvoton Technology Corporation of America, W83792AG Datasheet - Page 37

no-image

W83792AG

Manufacturer Part Number
W83792AG
Description
IC MONITOR H/W 48-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83792AG

Output Type
I²C™
Function
Hardware Monitor
Topology
ADC, Fan Control, Register Bank
Sensor Type
External
Sensing Temperature
External Sensor
Output Alarm
Yes
Output Fan
Yes
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Temperature Sensor Function
Temp Sensor
Resolution
10b
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83792AG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Company:
Part Number:
W83792AG
Quantity:
97
8.3
RESET Condition: Both VID detects no CPU, Resume Reset, INIT(CR40.7),
These registers are used to control 12 VID Pins. When power on, system can strap Pin14 to decide
which VRM table will be used later. This information is shown at CR14.VRM_CK. In VRM9, power on
value will be shown at VIDIN. When system wants to program VID pins, it must program a sequence
to CR16 first, the sequence is 5A, 73, B2, E0. After this, one can set EN_VIDO, and write VID to
output. To disable, write CR16 with A5, 4C, D9, 8A. In this way, the W83792D/G will lock its latest
status.
CR14/CR17 VID IN
Entry/Disable VID Output
7.VRD10
6.VRM_CK
6.AUTOUPD
5~0.VIDIN
Mnemonic
VID Control A
VID Control B
VID Control/Status Registers ⎯ Index 14h-18h (Bank 0)
VID IN A
VID IN B
Set to enable VRD10 table translation, clear to enable VRM9 table translation.
Default value is Inversion of VRM_CK.
Power on strapping value of Pin14, this will determine default value of VRD10 (bit 7).
Auto-update for VRD10.0 VID. In auto-update mode, VID is automatically update
and SMBus to modify upper/lower limit of vcore is not applicable. If programming
High/Low limit is required with VRD10=1, this bit must be cleared as 0.
Power-on value of VID pins(VRM9 mode) or current VID value on pins(VRM10
mode).
Bank Index Attr
0
0
0
0
0
16
14
15
17
18
RW
RW
RW
RO
RO
EN_VIDTG AUTOUPD VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0
ENTRYOK
EN_VIDO
EN_VIDO
VRD10
BIT 7
RW 0
RW
0
0
0
- 31 -
VRM_CK VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0
VIDCHG
VIDCHG
BIT 6
1 RW
RO
RO
RO
Write pattern/ Read 00h
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VID5
VID5
0
0
Publication Release Date: April 26, 2006
W83792AD/AG/D/G
VID4
VID4
0
0
VID3
VID3
0
0
RO
RO
VID2
VID2
0
0
VID1
VID1
ENTRY_ST
Revision 0.9
0
0
0
VID0
VID0
0
0
0

Related parts for W83792AG