MAX1533AETJ+ Maxim Integrated Products, MAX1533AETJ+ Datasheet - Page 32

• Manufacturer Part Number: MAX1533AETJ+
• Description: IC POWER SUPPLY CONTROLER 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1533AETJ+

• Applications: Power Supply Controller
• Voltage - Input: 4.5 ~ 26 V
• Current - Supply: 15µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
The 40/60 optimal interleaved architecture of the
MAX1533A/MAX1537A allows the input voltage to go
as low as 8.3V before the duty cycles begin to overlap.
This offers improved efficiency over a regular 180° out-
of-phase architecture where the duty cycles begin to
overlap below 10V. Figure 10 shows the input-capacitor
RMS current vs. input voltage for an application that
requires 5V/5A and 3.3V/5A. This shows the improve-
ment of the 40/60 optimal interleaving over 50/50 inter-
leaving and in-phase operation.
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for opti-
mal reliability and lifetime.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
The high-side MOSFET (N
the resistive losses plus the switching losses at both
Figure 10. Input RMS Current
32
I
RMS
______________________________________________________________________________________
=
INPUT RMS CURRENT FOR INTERLEAVED OPERATION
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION
(I
(I
D
I
OUT5
OUT5
RMS
LX5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
=
= I
- I
+ I
V
LOAD
6
IN
V
OUT3
OUT5
IN
)
2
50/50 INTERLEAVING
INPUT CAPACITOR RMS CURRENT
(D
(
- I
LX5
V
IN
8
OUT
)2 D
D
- D
LX3
(V
OL
OL
V
vs. INPUT VOLTAGE
=
IN
Power-MOSFET Selection
10
) + (I
IN
+ I
V
- V
V
OUT3
IN 2
IN
OUT
OUT3
IN PHASE
(1 - D
H
40/60 OPTIMAL
INTERLEAVING
12
)
) must be able to dissipate
V
- I
IN
)
IN
LX5
D
(V)
)
OL
2
14
(D
- D
= DUTY-CYCLE OVERLAP FRACTION
5V/5A AND 3.3V/5A
LX3
LX3
- D
+ D
16
OL
OL
) +
)
18
20
V
should be roughly equal to the losses at V
lower losses in between. If the losses at V
significantly higher, consider increasing the size of N
Conversely, if the losses at V
higher, consider reducing the size of N
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (N
possible on-resistance (R
ate-sized package (i.e., SO-8, DPAK, or D
reasonably priced. Ensure that the MAX1533A/
MAX1537A DL_ gate driver can supply sufficient cur-
rent to support the gate charge and the current injected
into the parasitic drain-to-gate capacitor caused by the
high-side MOSFET turning on; otherwise, cross-
conduction problems may occur. Switching losses are
not an issue for the low-side MOSFET since it is a zero-
voltage switched device when used in the step-down
topology.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
case power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
R
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (R
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N
it must allow for difficult-to-quantify factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
ing verification using a thermocouple mounted on N
IN(MIN)
DS(ON)
PD N
PD N
(
H
(
and V
required to stay within package power-dissi-
H
Switching
H
Re
) due to switching losses is difficult, since
IN(MAX)
sistive
DS(ON)
Power-MOSFET Dissipation
)
=
)
. Ideally, the losses at V
=
(
V
) losses. High-side switching
⎛
⎜
⎝
IN MAX
DS(ON)
V
(
OUT
V
IN
IN(MAX)
)
L
⎞
⎟
⎠
), comes in a moder-
)
) that has the lowest
(
2
I
LOAD
C
I
GATE
RSS
are significantly
)
H
2
H
2
. If V
R
f
IN(MAX)
PAK), and is
), the worst-
SW LOAD
DS ON
IN(MIN)
(
I
IN
IN(MIN)
H
) that
)
, with
does
H
are
:
H
.