HCTL-1101 Avago Technologies US Inc., HCTL-1101 Datasheet - Page 6

• Manufacturer Part Number: HCTL-1101
• Description: IC MOTION CONTROL GP 40DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-1101

• Applications: DC Motor Controller, Stepper Motor Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Number Of Outputs: -
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AC Electrical Characteristics
VDD = 5V + 5%; TA = -200C to +850C; Units + nsec
Note:
*General formula for determining AC characteristics for other clock frequencies (clk), between 100 kHz and 2 MHz.
6
ID #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Signal
Clock Period (clk)
Pulse Width, Clock High
Pulse Width, Clock Low
Clock Rise and Fall Time
Input Pulse Width RESET
Input Pulse Width STOP, LIMIT
Input Pulse Width INDEX
Input Pulse Width CHA, CHB
Delay CHA to CHB Transition
Input Rise/Fall Time
(CHA, CHB, INDEX)
Input Rise/Fall Time RESET, ALE, CS, OE,
STOP, LIMIT
Input Pulse Width ALE, CS
Delay Time, ALE Rise to CS Rise
Address Setup Time Before
ALE Fall/Rise
Address Setup Time Before
CS Fall/Rise
Write Data Setup Time Before CS Rise
Address/Data Hold Time
Setup Time, R/W Before CS Rise
Hold Time, R/W After CS Rise
Delay Time, Write Cycle, CS Rise to ALE Fall
Delay Time, Read/Write, CS Rise to CS Fall
Write Cycle, ALE Fall to ALE Fall
For Next Write
Delay Time, CS Rise to OE Fall
Delay Time, OE Fall to Data Bus Valid
Input Pulse Width OE
Hold Time, Data Held After OE Rise
Delay Time, Read Cycle, CS Rise to ALE Fall
Read Cycle, ALE Fall to ALE Fall
For Next Read
Output Pulse Width, PROF, INIT, Pulse, Sign,
PHA-PHD, MC Port
Output Rise/Fall Time, PROF, INIT, Pulse, Sign,
PHA-PHD, MC Port
Delay Time, Clock Rise to Output Rise
(PROF,INIT,PULSE,SIGN,PHASE)
Pulse Width, SYNC Low
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CPER
CPWH
CPWL
CR
IRST
IP
IX
IAB
AB
IABR
IR
IPW
CA
ASR1
ASR
DSR
H
WCS
WH
CSAL
CSCS
WC
CSOE
OEDB
IPWOE
DOEH
CSALR
RC
OF
OR
EP
SYNC
Clock Frequency
2 MHz
Min.
500
230
200
2500
600
1600
1600
600
80
50
20
20
20
20
20
20
1700
1500
1850
1700
100
1820
1950
500
10
9000
Max.
20
150
20
100
20
100
300
1 MHz
Min.
1000
300
200
5000
1100
3100
3100
1100
80
50
20
20
20
20
20
20
3400
3000
3700
3200
100
3320
3450
1000
20
18000
Max.
20
300
20
100
20
150
300
Formula*
Min.
200
5 clk
1 clk
+ 100 ns
3 clk
+ 100 ns
3 cl
+ 100 ns
1 clk
+ 100 ns
80
50
20
20
20
20
20
20
3.4 clk
3 clk
3.7 clk
3 clk
+ 200 ns
100
3 clk
+ 320 ns
3 clk
+ 450 ns
1 clk
10
18 clk
Max.
20
300(clk <
1 MHz)
20
100
20
150
300