TLE6240GP Infineon Technologies, TLE6240GP Datasheet - Page 20
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TLE6240GP
Manufacturer Part Number
TLE6240GP
Description
IC SW SMART 16-CH LOWSIDE PDSO36
Manufacturer
Infineon Technologies
Type
Low Sider
Datasheet
1.TLE6240GP.pdf
(37 pages)
Specifications of TLE6240GP
Input Type
SPI
Number Of Outputs
16
On-state Resistance
1 Ohm
Current - Output / Channel
300mA
Current - Peak Output
1.5A
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-36
Packages
PG-DSO-36
Thermal Class
Heatslug down
Id Nom
8 x 0.5, 8 x 1.0 A
Pin Count
36.0 Pins
Channels
16.0
Comment
inductive and resistive loads (e.g. injectors)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
SP000012171
TLE6240GPNT
TLE6240GPT
TLE6240GPT
TLE6240GPNT
TLE6240GPT
TLE6240GPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TLE6240GP
Manufacturer:
INF
Quantity:
5 510
Part Number:
TLE6240GP
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is
in a logic low state whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on
the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the
output stages.
The input data consist of 16 bit, made up of one control byte and one data byte. The control byte is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see
Chapter
6.2). The eight
data bits contain the input information for the eight channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a
high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin
following the rising edge of SCLK.
Data Sheet
20
Rev.3.3, 2010-02-15