TLE6240GP Infineon Technologies, TLE6240GP Datasheet - Page 18

• Manufacturer Part Number: TLE6240GP
• Description: IC SW SMART 16-CH LOWSIDE PDSO36
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE6240GP

• Input Type: SPI
• Number Of Outputs: 16
• On-state Resistance: 1 Ohm
• Current - Output / Channel: 300mA
• Current - Peak Output: 1.5A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Packages: PG-DSO-36
• Thermal Class: Heatslug down
• Id Nom: 8 x 0.5, 8 x 1.0 A
• Pin Count: 36.0 Pins
• Channels: 16.0
• Comment: inductive and resistive loads (e.g. injectors)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: SP000012171; TLE6240GPNT; TLE6240GPT; TLE6240GPT

5.5
Electrical Characteristics: SPI Interface
V
all voltages with respect to ground, positive current flowing into pin
Pos.
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
5.5.10
5.5.11
5.5.12
5.5.13
5.5.14
5.5.15
5.5.16
1) This parameter will not be tested but specified by design
2) This time is necessary between two write accesses to control e.g. channel 1 to 8 during the first access and channel 9 to
Data Sheet
S
= 4.5 V to 5.5 V,
16 during the second access. To get the correct diagnostic information, the transfer delay time has to be extended to the
maximum fault delay time
Parameter
Input Pull-down Current (SI, SCLK)
Input Pull-up Current (CS)
SO High State Output Voltage
SO Low State Output Voltage
Output Tri-state Leakage Current
Serial Clock Frequency
(depending on SO load)
Serial Clock Period (1/
Serial Clock High Time
Serial Clock Low Time
Enable Lead Time (falling edge of
CS to rising edge of CLK)
Enable Lag Time (falling edge of
CLK to rising edge of CS)
Data Setup Time (required time SI
to falling of CLK)
Data Hold Time (falling edge of
CLK to SI)
Disable Time (@
Transfer Delay Time
(CS high time between two
accesses)
Data Valid Time
SPI Interface
T
j
= -40 °C to +150 °C, Reset = H (unless otherwise specified)
C
t
d(fault)max
L
2)
= 50 pF)
f
clk
)
= 200 µs.
1)
Symbol
I
I
V
V
I
f
t
t
t
t
t
t
t
t
t
t
SCK
p(SCK)
SCKH
SCKL
lead
lag
SU
H
DIS
dt
valid
IN(SI,SCLK)
IN(CS)
SOlkg
SOH
SOL
18
Min.
10
10
V
–
-10
DC
200
50
50
200
200
20
20
–
200
–
–
–
S
- 0.4 –
Electrical and Functional Description of Blocks
Limit Values
Typ.
20
20
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
Smart 16-Channel Low-Side Switch
Max.
50
50
–
0.4
10
5
–
–
–
–
–
–
–
150
–
100
120
150
Unit
µA
µA
V
V
µA
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.3.3, 2010-02-15
Conditions
–
–
I
I
CS = H;
0 ≤
–
–
–
–
–
–
–
–
–
–
C
C
C
SOH
SOL
L
L
L
= 50 pF
= 100 pF
= 220 pF
V
= 2.5 mA
= 2 mA
SO
TLE6240GP
≤
V
1)
S
1)
1)