ISL6622BCRZ Intersil, ISL6622BCRZ Datasheet - Page 9

• Manufacturer Part Number: ISL6622BCRZ
• Description: IC MOSFET DRVR SYNC BUCK 10-DFN
• Manufacturer: Intersil

Specifications of ISL6622BCRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Minimize the inductance of the PHASE node: ideally, the
• Minimize the input current loop: connect the source of the
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
Upper MOSFET Self Turn-On Effect at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
coupling via the internal C
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
place a resistor (R
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
threshold of the upper MOSFET. A higher dV/dt, a lower
C
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 7 provides a visual reference for this
phenomenon and its potential solution.
ISL6622
ISL6622A
ISL6622B
DS
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
POWER RAILS
/C
GS
ratio, and a lower gate-source threshold upper
SOIC
SOIC
SOIC
DFN
DFN
DFN
GD
UGPH
/C
GS
) across the gate and source of the
GD
ratio, as well as the gate-source
of the MOSFET, the gate of the
Programmable
9
PSI = LOW
5.75V
Programmable
Separate Rail
Separate Rail
LVCC
5.75V
TABLE 2. ISL6622 FAMILY OPTIONS
PSI = HIGH
11.2V
11.2V
ISL6622B
Gate Drive Voltage Options
Intersil provides various gate drive voltage options in the
ISL6622 product family, as shown in Table 2.
The ISL6622 can drop the low-side MOSFET’s gate drive
voltage when operating in DEM, while the high-side FET’s
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
The ISL6622A allows the low-side MOSFET(s) to operate
from an externally-provided rail as low as 5V, eliminating the
LDO losses, while the high-side MOSFET’s gate drive voltage
of the DFN package can be connected to VCC or LVCC.
The ISL6622B sets the low-side MOSFET’s gate drive voltage
at a fixed, programmable LDO level, while the highside FETs’
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
V
V
R
R
GS_MILLER
GS_MILLER
FIGURE 7. GATE TO SOURCE RESISTOR TO REDUCE
UVCC
Separate Rail
Separate Rail
Separate Rail
=
=
R
R
UVCC
VCC
VCC
VCC
UGPH
UGPH
=
+
20kΩ
UPPER MOSFET MILLER COUPLING
=
+
R
dV
------- R C
R
dt
dV
------- R C
dt
GI
GI
⋅
Operating Voltage Ranges from 6.8V to 13.2V
⋅
⋅
⋅
C
C
rss
rss
UGATE
rss
rss
PHASE
BOOT
⎛
⎜
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎜
⎝
1 e
1 e
=
=
–
–
C
C
--------------------------------- -
dV
------- R C
dt
--------------------------------- -
dV
------ - R C
GD
GD
C
dt
BOOT
–
⋅
– DS
G
⋅
V
V
DS
VCC
⋅ iss
⋅
R
iss
G
C
C
C
⎞
⎟
⎟
⎟
⎟
⎠
GD
⎞
⎟
⎟
⎟
⎟
⎠
iss
iss
C
GS
=
=
C
C
March 19, 2009
VIN
GD
GD
Q
S
D
UPPER
(EQ. 5)
+
(EQ. 6)
+
C
C
C
DS
GS
GS