CY8CLEDAC02 Cypress Semiconductor Corp, CY8CLEDAC02 Datasheet - Page 5

• Manufacturer Part Number: CY8CLEDAC02
• Description: IC CTLR AC-DC DIMMABLE LED 8SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: High Power, AC Input, Dimmabler

Specifications of CY8CLEDAC02

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Supply: 8 V ~ 16 V
• Frequency: 200kHz
• Operating Temperature: -40°C ~ 85°C
• Number Of Outputs: 1
• Internal Switch(s): No
• Efficiency: 85%
• Topology: AC DC Offline Switcher
• Operating Supply Voltage: - 0.3 V to 18 V
• Maximum Supply Current: 20 mA
• Maximum Power Dissipation: 526 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Pin Count: 8
• Mounting: Surface Mount
• Operating Supply Voltage (max): 18V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Current - Output / Channel: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Functional Description
Overview
The digital logic block is the main control block. All the other
blocks are either inputs or outputs for the digital logic block.
The digital logic block receives signals to determine the input
voltage (V
output current (I
(current control), Output (flyback MOSFET gate drive control),
and Boost_Out (chopper MOSFET gate drive control).
The bias winding of the transformer provides voltage feedback
to the controller for regulation and safety features. The external
voltage sense resistors (not shown) determine the feedback
signal to the V
connects to circuitry composed of three comparators: V
(output overvoltage protection), V
switch), and V
V
detects an overvoltage condition, it will enter a shutdown mode
and wait for POR to re-initialize the system. V
by the control block to determine when the power in the flyback
MOSFET is at a minimum or in a 'valley'. When the V
voltage goes below the 0.128 V threshold the control block starts
monitoring valleys and will start the next cycle at the 'valley' for
maximum efficiency and minimum switching EMI. For normal
operation, the V
(1.538 V). When the V
controller senses an output overvoltage and tries to maintain a
constant output voltage. This is an intermediate mode where the
controller starts reacting to a problem with the output voltage.
However, an OVP fault will only trigger if V
exceeds V
The I
ators: I
together for soft start control and peak current detection,
overcurrent protection, and sense resistor short protection
respectively. The DAC V
stress associated with system startup. The I
monitors the voltage at the I
by current flowing through a small external resistor (R
not shown). When the I
the I
control block will shut off the output and wait for V
then start the next cycle. The V
side overcurrent protection. When the voltage on I
V
is detected, the control block will enter a shutdown mode and
reset the system. When the I
(0.16 V), a sense resistor short circuit fault is detected and the
control block will enter a shutdown mode and reset all the digital
logic.
The Output signal connects to the gate driver block for the
OUTPUT pin that, in turn, connects to the flyback MOSFET gate
pin (not shown). The OUTPUT pin is a digital control pin that
switches between high level (approximately V
(approximately ground). The duration for high (t
Document Number: 001-54879 Rev. *C
SENSE
PEAK
PEAK
SENSE
(1.9 V), the V
PEAK
voltage exceeds V
comparator asserts a high to the control block. The
IN
SENSE(MAX)
pin connects to circuitry composed of three compar-
), output voltage (V
, V
FB_C
SENSE
OCP
SENSE
SENSE
, and I
OCP
(voltage feedback from coil). When the
.
voltage should be set below V
SENSE
). It has three output controls; D
SENSE
pin of the controller. The V
signal gets asserted. When overcurrent
PEAK
SHORT_C
SENSE(MAX)
SENSE
voltage exceeds V
voltage reaches V
OCP
SENSE
SENSE
controls soft start; minimizing
pin. The voltage is generated
comparator provides primary
. These three blocks work
VMS
), temperature (V
(1.7 V) the control block
voltage reaches V
(voltage valley mode
CC
PEAK
VMS
SENSE(NOM)
REG-TH
SENSE
) and low level
SENSE
VMS
ON
is monitored
SENSE(NOM)
comparator
SENSE
) and low
detection;
ISENSE
reaches
(1.8 V),
voltage
T
ISENSE
), and
SENSE
RSNS
OVP
the
pin
-
(t
operating upon its inputs: V
and V
The Boost_Out signal connects to the gate driver block for the
BOOST pin that, in turn, connects to the chopper MOSFET gate
pin (not shown). The BOOST pin is again a digital control pin that
switches between high level (approximately V
(approximately ground). The BOOST pin timing is internally
controlled and depends on the mode of operation for the IC (that
is, no dimmer, trailing edge dimmer, or leading edge dimmer
mode).
The V
internal LDO, and an analog to digital converter. This pin can be
used for OTP along with automatic LED brightness adjustment
to compensate for temperature drift. This can be achieved by
simply connecting the V
shown). The current source causes a voltage to develop at the
V
the voltage is between 0.5 to 2 V, the controller operates
normally. For a voltage range 0.5 V to 0.3 V, the LED intensity is
linearly dimmed. At 0.3 V the LEDs are dimmed to 10 percent.
From 0.3 V to 0.1 V, the LED intensity stays at 10 percent and
below 0.1 V (V
shutdown mode, and reset all the digital logic.
Device Startup
Before startup, V
internal diode between V
on page 2). When the voltage at V
threshold V
In the first four AC half cycles after startup, the BOOST pin is held
high (see
dimmer type is detected and the AC line period is measured.
Following this, the controller enters an intermediate state and
waits for the output voltage to ramp up. When the output voltage
is higher than the forward voltage for the LED string, the
controller enters constant current mode.
An adaptive soft start control algorithm is applied at startup,
during which the initial output pulses are small and gradually get
larger until the full pulse width is achieved. The peak current is
limited cycle-by-cycle by I
If at any time the V
all the digital logic is reset. At this time the internal V
turns off allowing the V
If a faster startup is required, then an external active startup
scheme can be used. Components R10, R11, Q3, and D5 enable
active startup as illustrated in the
on page 14. Q3, a depletion type MOSFET, is initially on before
startup. The V
resistors R10 and R11 can be made much smaller than R3 and
R4 lowering the overall charging resistance. When V
above V
V
negative, thus turning Q3 off. This technique substantially
reduces startup time.
OFF
T
IN
pin which is sampled once every AC half cycle by the ADC. If
node low. The gate to source voltage across Q3 becomes
) of the Gate Driver is a function of the control block
CC
T
pin connects to a current source (I
CCST
.
Figure 3
CCST
, the internal control logic gets enabled pulling the
CC
SH-TH
, the control logic is enabled.
IN
CC
capacitor C8 charges a lot quicker as the
charges up the V
on page 6). During these half cycles the
), the controller will trigger a fault, enter
voltage drops below the V
CC
T
IN
pin to an external NTC component (not
PEAK
capacitor to charge for a fresh startup.
and V
IN
t
ON
comparator.
CC
, V
“Typical Application Diagram”
CC
FB
(see
CY8CLEDAC02
CC
, V
rises above the startup
“Logic Block Diagram”
VMS
capacitor through the
SD
), generated by an
, V
CC
CCUVL
T
) and low level
, I
Page 5 of 20
PEAK
threshold,
IN
CC
, V
switch
rises
OCP
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