PCA9634PW,118 NXP Semiconductors, PCA9634PW,118 Datasheet - Page 27
![IC LED DRIVER RGBA 20-TSSOP](/photos/6/52/65219/568-20-tssop_sot360-1_sml.jpg)
PCA9634PW,118
Manufacturer Part Number
PCA9634PW,118
Description
IC LED DRIVER RGBA 20-TSSOP
Manufacturer
NXP Semiconductors
Type
RGBA LED Driverr
Datasheet
1.PCA9634D118.pdf
(38 pages)
Specifications of PCA9634PW,118
Package / Case
20-TSSOP
Topology
Open Drain, PWM
Number Of Outputs
8
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
RGBA
Frequency
1MHz
Voltage - Supply
2.3 V ~ 5.5 V
Voltage - Output
5.5V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Current - Output / Channel
25mA
Internal Switch(s)
Yes
Low Level Output Current
25 mA
High Level Output Current
50 uA
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Supply Current
10 mA
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Efficiency
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4066-2
935282233118
PCA9634PW-T
PCA9634PW-T
935282233118
PCA9634PW-T
PCA9634PW-T
NXP Semiconductors
Table 17.
V
[1]
[2]
13. Dynamic characteristics
Table 18.
[1]
[2]
[3]
[4]
PCA9634_6
Product data sheet
Symbol
Address inputs
V
V
I
C
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
LI
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
DD
IL
IH
i
= 2.3 V to 5.5 V; V
V
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of SCL’s falling edge.
VD;ACK
VD;DAT
DD
must be lowered to 0.2 V in order to reset part.
SCL clock frequency
bus free time between a
STOP and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Parameter
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
Static characteristics
Dynamic characteristics
SS
= 0 V; T
amb
…continued
= 40 C to +85 C; unless otherwise specified.
Conditions
Conditions
Rev. 06 — 12 September 2008
[4][5]
[1]
[2]
[3]
[7]
Standard-mode
Min
250
4.7
4.0
4.7
4.0
0.3
0.3
4.7
4.0
0
0
-
-
-
I
2
C-bus
1000
Max
3.45
3.45
100
300
50
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode
Min
100
1.3
0.6
0.6
0.6
0.1
0.1
1.3
0.6
0
0
I
-
2
C-bus
Min
0.7V
-
0.5
1
b
b
[6]
[6]
8-bit Fm+ I
DD
Max
400
300
300
0.9
0.9
50
-
-
-
-
-
-
-
-
IL
of the SCL signal) in order to
Typ
-
-
-
3.7
Fast-mode Plus
0.26
0.26
0.26
0.05
0.05
0.26
Min
0.5
0.5
50
PCA9634
2
0
0
-
-
-
© NXP B.V. 2008. All rights reserved.
C-bus LED driver
I
2
C-bus
Max
+0.3V
5.5
+1
5
1000
Max
0.45
0.45
120
120
50
-
-
-
-
-
-
-
-
DD
27 of 38
Unit
V
V
pF
Unit
kHz
ns
ns
ns
ns
ns
A
s
s
s
s
s
s
s
s