LTC5100EUF#PBF Linear Technology, LTC5100EUF#PBF Datasheet - Page 33

• Manufacturer Part Number: LTC5100EUF#PBF
• Description: IC DRIVER VCSEL 3.2GBPS 16QFN
• Manufacturer: Linear Technology
• Type: Laser Diode Driverr

Specifications of LTC5100EUF#PBF

• Data Rate: 3.2Gbps
• Number Of Channels: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 54mA
• Current - Modulation: 12mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATIO
Microprocessor Controlled Operation
An external microprocessor or a test computer can take
full control of the LTC5100 by setting the Operating_mode
bit. When this bit is set, the LTC5100 stops searching for
an external EEPROM and takes commands from the mi-
croprocessor. It is even possible to combine standalone
and microprocessor controlled modes. If an EEPROM is
present, the LTC5100 will load its configuration registers
from the EEPROM at power-up. A microprocessor or test
computer can then read and write the LTC5100 registers
at will.
The primary purpose of the Operating_mode bit is to stop
the LTC5100’s EEPROM load attempts. Once the LTC5100
has loaded itself from an EEPROM (if present), it is not
Table 6. Effective Base Addresses for Various Sized EEPROMs
GENERIC PART NUMBER
Bits
Bytes
Device Address (Binary)
Word Address Space (Binary)
LTC5100 Generates
Device Address
LTC5100 Generates
Word Address
Effective Base Address
Comments
U
Minimum Size
Loads Every
0110_0000
0000_0000
xxxx_nnnn
1010_111.
Byte in the
EEPROM.
EEPROM.
1010xxx.
24LC00
= 0xAE
= 0x60
= 0x00
128
16
EEPROM Not Big
Enough for GBIC
Loads from 0x60
ID. LTC5100
xnnn_nnnn
0110_0000
0110_0000
1010_111.
24LC01B
1010xxx.
to 0x6F
= 0xAE
= 0x60
= 0x60
128
1k
Data and the GBIC ID.
0x60 to 0x6F, the First
technically necessary to set the Operating_mode bit to
communicate with the LTC5100.
The LTC5100 attempts to read the EEPROM every 64ms
until it successfully loads its registers or until the
Operating_mode bit is set. There is a finite chance that the
microprocessor and the LTC5100 will generate an I
collision if an EEPROM load attempt coincides with the
microprocessor’s attempt to access the LTC5100. In this
case, the microprocessor will receive a NACK (not-ac-
knowledged) response to its transmissions. The micro-
processor needs only to cease transmission in accordance
with the I
makes this second attempt within 64ms (typical), it is
guaranteed not to collide with the LTC5100.
LTC5100 Loads from
to Hold the LTC5100
That is Big Enough
Smallest EEPROM
16 Bytes of the
Standard GBIC
Vendor Area
nnnn_nnnn
0110_0000
0110_0000
1010_111.
EEPROM.
24LC02B
1010xxx.
= 0xAE
= 0x60
= 0x60
256
2k
2
C protocol and try again. If the microprocessor
0001_0110_0000
Outside the GBIC
LTC5100 Loads
from an Area
ID Data Area
nnnn_nnnn
0110_0000
1010_111.
24LC04B
1010.xxa
= 0x160
= 0xAE
= 0x60
512
4k
LTC5100
0111_0110_0000
Outside the GBIC
LTC5100 Loads
from an Area
ID Data Area
nnnn_nnnn
0110_0000
1010_111.
1010cba.
24LC16B
= 0x760
= 0xAE
= 0x60
2048
16k
sn5100 5100fs
33
2
C bus