ADE7754AR Analog Devices Inc, ADE7754AR Datasheet - Page 9

• Manufacturer Part Number: ADE7754AR
• Description: IC ENERY METER 3PHASE 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7754AR

• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD71049AR; AD71049AR

TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7754 is defined by the formula
Phase Error Between Channels
The HPF (high-pass filter) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
placed in the current channel. The phase correction network
ensures a phase match between the current channels and voltage
channels to within ± 0.1° over a range of 45 Hz to 65 Hz and
± 0.2° over a range of 40 Hz to 1 kHz. This phase mismatch
between the voltage and the current channels can be reduced
further with the phase calibration register in each phase.
Power Supply Rejection
This quantifies the ADE7754 measurement error as a percentage
of reading when power supplies are varied. For the ac PSR mea-
surement, a reading at nominal supplies (5 V) is taken. A second
reading is obtained using the same input signal levels when an ac
(175 mV rms/100 Hz) signal is introduced onto the supplies. Any
error introduced by this ac signal is expressed as a percentage of
reading. See the Measurement Error definition above.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained using the same
input signal levels when the power supplies are varied ± 5%. Any
error introduced is again expressed as a percentage of reading.
ADC Offset Error
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a dc analog input signal. The magni-
tude of the offset depends on the gain and input range selection
(see the TPCs). However, when HPFs are switched on, the
offset is removed from the current channels and the power
calculation is unaffected by this offset.
Gain Error
The gain error in the ADE7754 ADCs is defined as the differ-
ence between the measured ADC output code (minus the
offset) and the ideal output code. See the Current Channel
ADC and the Voltage Channel ADC sections. The difference is
expressed as a percentage of the ideal code.
Gain Error Match
Gain error match is defined as the gain error (minus the offset)
obtained when switching between a gain of 1, 2, or 4. It is
expressed as a percentage of the output ADC code obtained
under a gain of 1.
POWER SUPPLY MONITOR
The ADE7754 contains an on-chip power supply monitor. The
analog supply (AV
If the supply is less than 4 V ± 5%, the ADE7754 goes into an
inactive state (i.e., no energy is accumulated when the supply
voltage is below 4 V). This is useful to ensure correct device
operation at power-up and during power-down. The power sup-
ply monitor has built-in hysteresis and filtering, providing a high
degree of immunity to false triggering due to noisy supplies.
REV. 0
Percentage Error



Energy
Re
gistered by ADE
DD
) is continuously monitored by the ADE7754.
=
True Energy
7754
−
True Energy
×
100%



–9–
The RESET bit in the interrupt status register is set to Logic 1
when AV
masked by the interrupt enable register and cannot cause the
IRQ pin to go low. The power supply and decoupling for the
part should ensure that the ripple at AV
± 5% as specified for normal operation.
ANALOG INPUTS
The ADE7754 has six analog inputs, divisible into two chan-
nels: current and voltage. The current channel consists of three
pairs of fully differential voltage inputs: I
I
mum differential voltage of ± 0.5 V. The voltage channel has
three single-ended voltage inputs: V
single-ended voltage inputs have a maximum input voltage of
± 0.5 V with respect to V
voltage channel have a PGA (programmable gain amplifier) with
possible gain selections of 1, 2, or 4. The same gain is applied to
all the inputs of each channel.
The gain selections are made by writing to the gain register. Bits 0
and 1 select the gain for the PGA in the fully differential current
channel. The gain selection for the PGA in the single-ended volt-
age channel is made via Bits 5 and 6. Figure 5 shows how a gain
selection for the current channel is made using the gain register.
STATUS REGISTER
CP
THE INTERRUPT
READ RSTATUS
, I
RESET FLAG IN
CN
POWER-ON
REGISTER
. The fully differential voltage input pairs have a maxi-
Figure 4. On-Chip Power Supply Monitoring
DD
AV
DD
drops below 4 V ± 5%. The RESET flag is always
I
I
AN
AP
5V
4V
0V
Figure 5. PGA in Current Channel
, I
, I
BN
BP
, I
, I
V
CP
CN
IN
N
. Both the current channel and the
GAIN[7:0]
ACTIVE
TIME
k
AP
, V
V
IN
DD
AP
BP
, I
does not exceed 5 V
, and V
GAIN (k)
SELECTION
INACTIVE
AN
ADE7754
; I
BP
CP
, I
. These
BN
; and