ADE7754AR Analog Devices Inc, ADE7754AR Datasheet - Page 10

• Manufacturer Part Number: ADE7754AR
• Description: IC ENERY METER 3PHASE 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7754AR

• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD71049AR; AD71049AR

ADE7754
Figure 6 shows how the gain settings in PGA 1 (current channel)
and PGA 2 (voltage channel) are selected by various bits in the
gain register. The no-load threshold and sum of the absolute
value can also be selected in the gain register. See Table X.
ANALOG-TO-DIGITAL CONVERSION
The ADE7754 carries out analog-to-digital conversion using
second order Σ-∆ ADCs. The block diagram in Figure 7 shows a
first order (for simplicity) Σ-∆ ADC. The converter is made up of
two parts, the Σ-∆ modulator and the digital low-pass filter.
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7754, the sampling clock is equal to CLKIN/12.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal.
If the loop gain is high enough, the average value of the DAC
output (and therefore the bit stream) will approach that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless. Only
when a large number of samples are averaged will a meaningful
result be obtained. This averaging is carried out in the second part
of the ADC, the digital low-pass filter. Averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling; the signal is sampled at a rate (frequency)
many times higher than the bandwidth of interest. For example,
the sampling rate in the ADE7754 is CLKIN/12 (833 kHz),
and the band of interest is 40 Hz to 2 kHz. Oversampling
LOW-PASS FILTER
PGA 2 GAIN SELECT
00 =
01 =
10 =
ANALOG
R
1
2
4
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS
RESERVED = 0 RESERVED = 0
CURRENT AND VOLTAGE CHANNEL PGA CONTROL
C
Figure 7. First Order ( - ) ADC
7
0
Figure 6. Analog Gain Register
+
6
0
–
GAIN REGISTER*
5
0
INTEGRATOR
4
0
V
NO LOAD
3
0
REF
1-BIT DAC
ABS
2
0
....10100101......
MCLK/12
1
0
LATCHED
COMPARATOR
0
0
PGA 1 GAIN SELECT
00 =
01 =
10 =
ADDR: 18h
1
1
2
4
LOW-PASS
DIGITAL
FILTER
24
–10–
spreads the quantization noise (noise due to sampling) over a
wider bandwidth. With the noise spread more thinly over a
wider bandwidth, the quantization noise in the band of interest
is lowered. See Figure 8.
Oversampling alone is not an efficient enough method to
improve the signal to noise ratio (SNR) in the band of interest.
For example, an oversampling ratio of 4 is required to increase
the SNR by only 6 dB (1 bit). To keep the oversampling ratio at
a reasonable level, the quantization noise can be shaped so that
most of the noise lies at the higher frequencies. In the Σ-∆
modulator, the noise is shaped by the integrator, which has a
high-pass type of response for the quantization noise. The result
is that most of the noise is at the higher frequencies, where it
can be removed by the digital low-pass filter. This noise shaping
is shown in Figure 8.
Antialias Filter
Figure 7 shows an analog low-pass filter (RC) on the input to
the modulator. This filter is used to prevent aliasing, an artifact
of all sampled systems. Frequency components in the input
signal to the ADC that are higher than half the sampling rate of
the ADC appear in the sampled signal at a frequency below half
the sampling rate. Figure 9 illustrates the effect; frequency com-
ponents (arrows shown in black) above half the sampling
frequency (also known as the Nyquist frequency), i.e., 417 kHz,
get imaged or folded back down below 417 kHz (arrows shown
in gray). This happens with all ADCs, regardless of the archi-
tecture. In the example shown, only frequencies near the sampling
frequency, i.e., 833 kHz, will move into the band of interest for
metering, i.e., 40 Hz to 2 kHz. This allows use of a very simple
LPF (low-pass filter) to attenuate these high frequencies (near
900 kHz) and thus prevent distortion in the band of interest. A
simple RC filter (single pole) with a corner frequency of 10 kHz
produces an attenuation of approximately 40 dBs at 833 kHz.
See Figure 9. This is sufficient to eliminate the effects of aliasing.
SIGNAL
SIGNAL
NOISE
NOISE
Figure 8. Noise Reduction Due to Oversampling
and Noise Shaping in the Analog Modulator
0
0
2
2
OUTPUT FROM DIGITAL
HIGH RESOLUTION
DIGITAL FILTER
LPF
FREQUENCY (kHz)
FREQUENCY (kHz)
ANTIALIAS FILTER (RC)
417
417
SHAPED
NOISE
SAMPLING
FREQUENCY
833
833
REV. 0