ADE7754AR Analog Devices Inc, ADE7754AR Datasheet - Page 39

• Manufacturer Part Number: ADE7754AR
• Description: IC ENERY METER 3PHASE 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7754AR

• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD71049AR; AD71049AR

Interrupt Enable Register (0Fh)
When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the enable bit for this event is Logic 1 in this
register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table XVI describes the
function of each bit in the interrupt enable register.
Bit
Location
0
1
2
3
4
5
6
7
8
9
Ah
Bh
Ch
Dh
Eh
Fh
REV. 0
(END OF THE LAENERGY AND LVAENERGY ACCUMULATION)
(APPARENT ENERGY REGISTER HALF FULL)
Interrupt
Flag
AEHF
SAGA
SAGB
SAGC
ZXTOA
ZXTOB
ZXTOC
ZXA
ZXB
ZXC
LENERGY
PKV
PKI
WFSM
VAEHF
(CURRENT CHANNEL PEAK DETECTION)
(VOLTAGE CHANNEL PEAK DETECTION)
(NEW WAVEFORM SAMPLE READY)
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register
(i.e., the AENERGY register is half-full).
Enables an interrupt when there is a SAG on the line voltage of the Phase A.
Enables an interrupt when there is a SAG on the line voltage of the Phase B.
Enables an interrupt when there is a SAG on the line voltage of the Phase C.
Enables an interrupt when there is a zero-crossing timeout detection on Phase A.
Enables an interrupt when there is a zero-crossing timeout detection on Phase B.
Enables an interrupt when there is a zero-crossing timeout detection on Phase C.
Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase A—
zero-crossing detection.
Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase B—
zero-crossing detection.
Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase C—
zero-crossing detection.
Enables an interrupt when the LAENERGY and LVAENERGY accumulations over LINCYC
are finished.
Reserved.
Enables an interrupt when the voltage input selected in the MMODE register is above the
value in the PKVLVL register.
Enables an interrupt when the current input selected in the MMODE register is above the
value in the PKILVL register.
Enables an interrupt when a data is present in the waveform register.
Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY register
(i.e., the VAENERGY register is half full).
VAEHF
LENERGY
WFSM
F
0
PKI
PKV
E
0
RESERVED
0
D
Table XVI. IRQEN Register
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS
C
0
B
0
INTERRUPT ENABLE REGISTER*
A
0
–39–
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ZX
(ZERO-CROSSING TIMEOUT DETECTION)
AEHF
(ACTIVE ENERGY REGISTER HALF FULL)
SAG
(SAG EVENT DETECT)
ZX
(ZERO-CROSSING DETECTION)
0
0
ADDR: 0Fh
ADE7754