MB39A132QN-G-ERE1 Fujitsu Semiconductor America Inc, MB39A132QN-G-ERE1 Datasheet - Page 36

• Manufacturer Part Number: MB39A132QN-G-ERE1
• Description: IC CONV DC-DC LI-ION 32QFN
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of MB39A132QN-G-ERE1

• Function: Charge Management
• Battery Type: Lithium-Ion (Li-Ion)
• Operating Temperature: 25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1020

MB39A132
36
• SWFET selection
If MB39A132 is used for the charger for a notebook PC, since the output voltage of an AC adapter, which is
the input voltage of an SWFET, is 25 V or less, in general, a 30 V class MOS FET can be used as the SWFET.
Obtain the maximum value of the current flowing through the SWFET in order to determine whether the
current flowing through the SWFET is within the rated value. The maximum current flowing through the
SWFET can be found by the following formula.
In addition, find the loss of the SWFET in order to determine whether the allowable loss of the SWFET is
within the rated value. The allowable loss of the high-side of FET can be found by the following formula.
P
FET continuity loss of high-side
FET switching loss of high-side
HisideFET
P
I
P
DMAX
RON_Hiside
I
I
ΔIL : Inductor ripple current peak to peak value [A]
P
P
P
P
I
V
V
R
P
V
f
Ibtm
DMAX
OMAX
OMAX
SW_Hiside
OSC
O
HisideFET
RON_Hiside
SW_Hiside
RON_Hiside
IN
SW_Hiside
IN
ON_Hiside
≥ Io
= P
: Maximum SWFET drain current [A]
: Maximum charge current [A]
MAX
= I
=
RON_Hiside
: FET loss of high-side [W]
: FET switching loss of high-side [W]
: FET continuity loss of high-side [W]
: FET switching loss of high-side [W]
: Switching power supply voltage [V]
: Switching frequency (Hz)
: Bottom value of ripple current of inductor [A]
: FET continuity loss of high-side [W]
: Maximum charge current [A]
: Switching power supply voltage [V]
: Output voltage [V]
: FET ON resistance of high-side [Ω]
OMAX
+
V
IN
2
× f
×
ΔIL
2
+ P
OSC
V
V
SW_Hiside
IN
O
× (Ibtm × Tr + Itop × Tf)
× R
2
ON_Hiside
DS04–27265–3E