NCP1216AP100G ON Semiconductor, NCP1216AP100G Datasheet - Page 14

• Manufacturer Part Number: NCP1216AP100G
• Description: IC CTRLR PWM CM OTP HV 8DIP
• Manufacturer: ON Semiconductor

Specifications of NCP1216AP100G

• Output Isolation: Isolated
• Frequency Range: 90 ~ 110kHz
• Voltage - Input: 10 ~ 16 V
• Operating Temperature: 0°C ~ 150°C
• Package / Case: 8-DIP (0.300", 7.62mm), 7 Leads
• Duty Cycle (max): 50 %
• Mounting Style: Through Hole
• Switching Frequency: 110 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 20 ns
• Rise Time: 60 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a V
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at V
stuck until V
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (−2 * V
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
Dt + DV·C
Simple and inexpensive cures exist to prevent from
i
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence
CC
CC
reaches 5.6 V: we are in latchoff phase.
fall time of 10 ms could be well
f
0
) due to the diode bridge. Also,
CC
V
= 10 V and it remains
5 V/DIV
10 ms/DIV
CC
(eq. 19)
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14
Protecting the Controller Against Negative Spikes
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between V
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its V
and keeps activating the MOSFET ON and OFF with a peak
current limited by R
coefficient Q of the resonating network formed by L
C
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its V
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal V
from V
VCC
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
bulk
As with any controller built upon a CMOS technology, it
Another option (Figure 28) consists in wiring a diode
CC
ON
is low (e.g. the MOSFET R
capacitor. If this V
CC
CC
sooner and thus stops the switching activity before
discharge testifies for latchup.
to the bulk capacitor to force V
V
1 V/DIV
latch
CC
and GND. If the current sense pin is
sense
CC
. Unfortunately, if the quality
capacitor is of sufficient value,
dson
+ R
sense
CC
CC
are small),
capacitor
to reach
p
and