EPCS16SI16N Altera, EPCS16SI16N Datasheet - Page 28
![IC CONFIG DEVICE 16MBIT 16-SOIC](/photos/7/31/73169/544-16-soic_sml.jpg)
EPCS16SI16N
Manufacturer Part Number
EPCS16SI16N
Description
IC CONFIG DEVICE 16MBIT 16-SOIC
Manufacturer
Altera
Series
EPCSr
Specifications of EPCS16SI16N
Programmable Type
In System Programmable
Memory Size
16Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.50mm Width)
Memory Type
Flash
Clock Frequency
20MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
16
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1240-5
EPCS16SI16
EPCS16SI16
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPCS16SI16N
Manufacturer:
ALTERA
Quantity:
1 250
Company:
Part Number:
EPCS16SI16N
Manufacturer:
ALTERA44
Quantity:
540
Part Number:
EPCS16SI16N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
3–28
Table 3–16. Write Operation Parameters (Part 2 of 2)
Figure 3–19. Read Operation Timing
Volume 2: Configuration Handbook
t
t
t
t
t
t
t
t
Note to
(1) These parameters are not shown in
NCSH
DSU
DH
CSH
WB
WS
EB
ES
(1)
(1)
Symbol
(1)
(1)
Table
3–16:
DCLK
DATA
ASDI
nCS
Chip select (nCS) hold time
Data (ASDI) in setup time before rising edge on DCLK
Data (ASDI) hold time after rising edge on DCLK
Chip select high time
Write bytes cycle time for EPCS1, EPCS4, EPCS16, and
EPCS64
Write bytes cycle time for EPCS128
Write status cycle time
Erase bulk cycle time for EPCS1
Erase bulk cycle time for EPCS4
Erase bulk cycle time for EPCS16
Erase bulk cycle time for EPCS64
Erase bulk cycle time for EPCS128
Erase sector cycle time for EPCS1, EPCS4, EPCS16,
and EPCS64
Erase sector cycle time for EPCS128
Add_Bit 0
Figure 3–19
operation.
Table 3–17
operation.
Table 3–17. Read Operation Parameters
f
t
t
t
t
RCLK
CH
CL
ODIS
nCLK2D
Symbol
t
nCLK2D
Figure
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
defines the serial configuration device timing parameters for read
Bit N
shows the timing waveform for the serial configuration device's read
Parameter
3–18.
Read clock frequency (from FPGA or
embedded processor) for read bytes
operation
DCLK high time
DCLK low time
Output disable time after read
Clock falling edge to data
Bit N 1
Parameter
t
CL
Min
100
10
—
—
—
—
—
—
—
—
—
—
5
5
t
CH
Min
Bit 0
—
25
25
—
—
Typ
105
1.5
2.5
—
—
—
—
17
68
5
3
5
2
2
June 2011 Altera Corporation
t
ODIS
Max
20
—
—
15
Max
8
160
250
15
40
—
—
—
—
10
6
5
7
3
6
Timing Information
MHz
Unit
Unit
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
s
s
s
s
s
s
s