EPCS16SI16N Altera, EPCS16SI16N Datasheet - Page 24

• Manufacturer Part Number: EPCS16SI16N
• Description: IC CONFIG DEVICE 16MBIT 16-SOIC
• Manufacturer: Altera
• Series: EPCSr

Specifications of EPCS16SI16N

• Programmable Type: In System Programmable
• Memory Size: 16Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Memory Type: Flash
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1240-5; EPCS16SI16

3–24
Figure 3–14. Read Device Identification Operation Timing Diagram
Note to
(1) Only EPCS128 supports read device identification operation.
Volume 2: Configuration Handbook
Figure
DCLK
ASDI
DATA
nCS
3–14:
Write Bytes Operation
The write bytes operation code is b'0000 0010, with the MSB listed first. The write
bytes operation allows bytes to be written to the memory. The write enable operation
must be executed prior to the write bytes operation to set the write enable latch bit in
the status register to 1.
The write bytes operation is implemented by driving nCS low, followed by the write
bytes operation code, three address bytes and a minimum one data byte on ASDI. If
the eight least significant address bits (A[7..0]) are not all 0, all sent data that goes
beyond the end of the current page is not written into the next page. Instead, this data
is written at the start address of the same page (from the address whose eight LSBs are
all 0). Drive nCS low during the entire write bytes operation sequence, as shown in
Figure
If more than 256 data bytes are shifted into the serial configuration device with a write
bytes operation, the previously latched data is discarded and the last 256 bytes are
written to the page. However, if less than 256 data bytes are shifted into the serial
configuration device, they are guaranteed to be written at the specified addresses and
the other bytes of the same page are unaffected.
If the design must write more than 256 data bytes to the memory, it needs more than
one page of memory. Send the write enable and write bytes operation codes followed
by three new targeted address bytes and 256 data bytes before a new page is written.
nCS must be driven high after the eighth bit of the last data byte has been latched in.
Otherwise, the device will not execute the write bytes operation. The write enable
latch bit in the status register is reset to 0 before the completion of each write bytes
operation. Therefore, the write enable operation must be carried out before the next
write bytes operation.
The device initiates the self-timed write cycle immediately after nCS is driven high.
Refer to t
respective EPCS devices. Therefore, you must account for this amount of delay before
another page of memory is written. Alternatively, you can check the status register’s
write in progress bit by executing the read status operation while the self-timed write
cycle is in progress. The write in progress bit is set to 1 during the self-timed write
cycle, and 0 when it is complete.
0
High Impedance
1
2
3–15.
Operation Code
WB
3
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
in
4
Table 3–16 on page 3–27
5
6
7
MSB
15
8
14
9
13
10
Two Dummy Bytes
3
20
for the self-timed write cycle time for the
(Note 1)
2
21
1
23
0
24
MSB
7
25
6
26
Serial Configuration Device Memory Access
5
27
4
28
Silicon ID
3
29
June 2011 Altera Corporation
2
30
1
31
0
32