IDT71024S15TY IDT, Integrated Device Technology Inc, IDT71024S15TY Datasheet - Page 6

• Manufacturer Part Number: IDT71024S15TY
• Description: IC SRAM 1MBIT 15NS 32SOJ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71024S15TY

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 1M (128K x 8)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOJ
• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 71024S15TY

Timing Waveform of Write Cycle No. 2
(CS
NOTES:
1. A write occurs during the overlap of a LOW CS
2. t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
ADDRESS
both be active during the t
on the bus for the required t
ADDRESS
WR
DATA
1
DATA
is measured from the earlier of either CS
DATA
AND CS
CS
CS
1
OUT
CS
CS
WE
LOW transition or the CS
WE
IN
2
IN
1
2
1
CW
DW
2
write period.
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
Controlled Timing)
2
HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS
t
AS
t
AS
1
or WE going HIGH or CS
1
(3)
, HIGH CS
(1,4,6)
2
, and a LOW WE.
t
t
WHZ
CW
(5)
2
going LOW to the end of the write cycle.
t
t
AW
AW
WP
(1,4)
must be greater than or equal to t
t
t
WC
WP
t
6.42
t
CW
WC
6
(6)
HIGH IMPEDANCE
t
t
DW
DATA
DW
DATA
IN
Commercial and Industrial Temperature Ranges
WHZ
VALID
IN
VALID
+ t
DW
t
DH
t
to allow the I/O drivers to turn off and data to be placed
t
t
WR
OW
WR
(2)
(2)
(5)
t
DH
(3)
t
CHZ
WP
2964 drw 08
1
(5)
2964 drw 07
.
and CS
2
must