CY7C1339G-133AXET Cypress Semiconductor Corp, CY7C1339G-133AXET Datasheet - Page 5

• Manufacturer Part Number: CY7C1339G-133AXET
• Description: IC SRAM 4MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339G-133AXET

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05520 Rev. *F
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
signals. The CY7C1339G provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
ZZ Mode Electrical Characteristics
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
1
, CE
[A:D]
into
[A:D]
) are asserted active to conduct a Write to the
2
, CE
) input, will selectively write to only the desired
the
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
3
address
are all asserted active. The address
1
, CE
2
, CE
register
3
Description
are all asserted active, and
and
the
[A:D]
address
) and
[A:D]
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1339G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
Address
Address
Test Conditions
DD
DD
A1, A0
A1, A0
First
First
00
01
10
00
01
10
11
11
– 0.2V
– 0.2V
Address
Address
Second
Second
A1, A0
A1, A0
01
00
11
10
01
10
11
00
1
, CE
2
, CE
DD
2t
Min.
CYC
0
)
Address
Address
3
A1, A0
A1, A0
, ADSP, and ADSC must
Third
Third
ZZREC
10
00
01
10
00
01
11
11
CY7C1339G
2t
2t
Max.
40
CYC
CYC
after the ZZ input
Page 5 of 18
Address
Address
Fourth
Fourth
A1, A0
A1, A0
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns
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