CY7C1339G-133AXET Cypress Semiconductor Corp, CY7C1339G-133AXET Datasheet
CY7C1339G-133AXET
Specifications of CY7C1339G-133AXET
Available stocks
Related parts for CY7C1339G-133AXET
CY7C1339G-133AXET Summary of contents
Page 1
... Cypress Semiconductor Corporation Document #: 38-05520 Rev. *F 4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
Page 2
... D DQ BYTE SSQ V 27 DDQ Document #: 38-05520 Rev. *F 250 MHz 200 MHz 166 MHz 2.6 2.8 325 265 40 40 100-Pin TQFP Pinout CY7C1339G CY7C1339G 133 MHz Unit 3.5 4.0 ns 240 225 DDQ V SSQ DQ B BYTE SSQ V DDQ DDQ V SSQ BYTE SSQ V ...
Page 3
... CLK BWE MODE NC/72M Description 1 to select/deselect the device. ADSP is ignored select/deselect the device.CE is sampled only when a new external address select/deselect the device sampled only when a new external address CY7C1339G DDQ NC/9M NC/576M A NC/ DDQ DDQ DDQ NC/36M DDQ , CE , and CE are sampled active. A1, A0 ...
Page 4
... Maximum access delay from the clock rise (t (250-MHz device). The CY7C1339G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
Page 5
... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339G is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE ...
Page 6
... and BWE = L or GW= L. WRITE = H when all Byte write enable signals and CE 1 CY7C1339G ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State L L-H Tri-State L-H Tri-State L-H ...
Page 7
... Write Bytes D, C Write Bytes Write Bytes Write All Bytes Write All Bytes Note: 8.Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05520 Rev BWE valid. Appropriate write will be done based on which byte write is active. X CY7C1339G Page [+] Feedback ...
Page 8
... Max, Device Deselected, All speeds ≤ 0. > V – 0.3V, IN DDQ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1339G + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V 2.5V –5% –5%/+10 Min. Max. Unit 3 ...
Page 9
... SCOPE ( 1667Ω 1667Ω 2.5V 2. DDQ DDQ OUTPUT OUTPUT GND GND 1538Ω 1538Ω INCLUDING INCLUDING JIG AND JIG AND (b) (b) SCOPE SCOPE CY7C1339G Min. Max. 105 TQFP BGA Package Package Unit TQFP BGA Package Package Unit °C/W 30.32 34.1 ° ...
Page 10
... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1339G –166 –133 Max. Min. Max. Min. Max. Unit 6.0 7 ...
Page 11
... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1339G A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
Page 12
... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05520 Rev. *F ADSC extends burst A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. [A:D] CY7C1339G t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE Page ...
Page 13
... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21 HIGH. Document #: 38-05520 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1339G A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
Page 14
... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05520 Rev DDZZ High-Z DON’T CARE CY7C1339G t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
Page 15
... CY7C1339G-133BGI CY7C1339G-133BGXI CY7C1339G-133AXE 166 CY7C1339G-166AXC CY7C1339G-166BGC CY7C1339G-166BGXC CY7C1339G-166AXI CY7C1339G-166BGI CY7C1339G-166BGXI 200 CY7C1339G-200AXC CY7C1339G-200BGC CY7C1339G-200BGXC CY7C1339G-200AXI CY7C1339G-200BGI CY7C1339G-200BGXI 250 CY7C1339G-250AXC CY7C1339G-250BGC CY7C1339G-250BGXC CY7C1339G-250AXI CY7C1339G-250BGI CY7C1339G-250BGXI Document #: 38-05520 Rev. *F www.cypress.com for actual products offered. Package Diagram Package Type 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array ( ...
Page 16
... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1339G 1.40±0.05 12°±1° SEE DETAIL (8X) ...
Page 17
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 119-Ball BGA ( 2.4 mm) (51-85115) Ø1.00(3X) REF 0.15(4X) CY7C1339G Ø0. Ø0. Ø0.75±0.15(119X ...
Page 18
... Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM Document Number: 38-05520 Orig. of REV. ECN NO. Issue Date Change ** 224368 See ECN RKF *A 288909 See ECN VBL *B 332895 See ECN SYT *C 351194 See ECN PCI *D 366728 See ECN PCI ...