M95640-WMN6P STMicroelectronics, M95640-WMN6P Datasheet
M95640-WMN6P
Specifications of M95640-WMN6P
M95640-WMN6P
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M95640-WMN6P Summary of contents
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Features ■ Compatible with SPI bus serial interface (positive clock SPI modes) ■ Single supply voltage: – 4.5 to 5.5 V for M95320 – 2.5 to 5.5 V for M95320-W – 1.8 to 5.5 V for M95320-R ■ 10 MHz, ...
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... Supply voltage (V 4.1.1 4.1.2 4.1.3 4.1.4 4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.1 4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage V CC ...
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... M95320, M95320-W, M95320-R 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. ...
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... Description 1 Description The M95320, M95320-W and M95320-R are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The devices are 32 Kbit devices organized as 4096 × 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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M95320, M95320-W, M95320-R Table 1. Signal names Signal name HOLD Description Serial Clock Serial data input Serial data output Chip Select Write Protect Hold Supply voltage Ground Doc ID 5711 Rev ...
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Signal description 2 Signal description During all operations (min (max All of the input and output signals must be held high or low (according to voltages ...
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... M95320, M95320-W, M95320-R 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write operations. ...
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... All output data bytes are shifted out of the device, most significant bit first. The Serial Data output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. ...
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M95320, M95320-W, M95320-R 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched ...
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... Supply voltage (V 4.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V Table 10). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t ...
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M95320, M95320-W, M95320-R 4.1.4 Power-down During power-down (continuous decrease in the V V operating voltage defined in CC ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (there should ...
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... Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion ● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. ● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the Status Register ...
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... M95320, M95320-W, M95320-R 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Address Register Figure 6. High Voltage Control Logic I/O Shift Register and Counter Doc ID 5711 Rev 12 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only ...
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... It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 7. Write Enable (WREN) sequence 16/44 Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array 7, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance ...
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M95320, M95320-W, M95320-R 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted ...
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... The Status Register format is shown in Register are as follows: 6.3.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. 6.3.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch ...
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M95320, M95320-W, M95320-R Figure 9. Read Status Register (RDSR) sequence 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, ...
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... Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification ...
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... When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle ...
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... Figure 12. Byte Write (WRITE) sequence Depending on the memory size, as shown in 22/44 12, to send this instruction to the device, Chip Select (S) is first driven Figure 12, this occurs after the eighth bit of the data byte has been to Table ...
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... M95320, M95320-W, M95320-R Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown Instruction 16-Bit Address Data Byte 2 Data Byte Table 6, the most significant address bits are Don’t Care. Doc ID 5711 Rev Data Byte Data Byte Instructions AI01796D 23/44 ...
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... Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0. 24/44 M95320, M95320-W, M95320-R ...
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... These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. ...
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DC and AC parameters 9 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from ...
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M95320, M95320-W, M95320-R Figure 14. AC measurement I/O waveform Table 12. Capacitance Symbol C Output capacitance (Q) OUT C Input capacitance (D) IN Input capacitance (other pins) 1. Sampled only, not 100% tested. Table 13. DC characteristics (M95320, device grade ...
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DC and AC parameters Table 14. DC characteristics (M95320-W, device grade 6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current I CC1 (Standby) V Input low voltage IL V Input ...
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M95320, M95320-W, M95320-R Table 16. DC characteristics (M95320-R) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CCR I Supply current (Standby) CC1 V Input low voltage IL V Input high voltage IH ...
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DC and AC parameters Table 17. AC characteristics (M95320, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH ...
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M95320, M95320-W, M95320-R Table 18. AC characteristics (M95320-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ...
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DC and AC parameters Table 19. AC characteristics (M95320-W, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH ...
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M95320, M95320-W, M95320-R Table 20. AC characteristics (M95320-R) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( ...
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DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/44 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 5711 Rev ...
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M95320, M95320-W, M95320-R Figure 17. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 5711 Rev 12 DC and AC parameters tSHSL tSHQZ AI01449f 35/44 ...
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Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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M95320, M95320-W, M95320-R Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol ...
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Package mechanical data Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline A 1. Drawing is not to scale. 2. The central pad (the area the above illustration) is ...
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M95320, M95320-W, M95320-R 11 Part numbering Table 24. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 320 = 32 Kbit (4096 × 8) Operating voltage blank = V = 4 ...
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Part numbering Table 25. Available M95320x products (package, voltage range, temperature grade) Package SO8 (MN) TSSOP (DW) MLP 2 × (MB) 40/44 M95320 M95320-W 4 5 5.5 V Range 6 Range 3 ...
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... I O 4.0 TSSOP8 connections added to DIP and SO connections M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and related characteristics added. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect Product List summary table added ...
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... I and I parameters modified in CC CC1 (M95320-W, device grade Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz MHz in the device grade 6 T characteristics (M95320-W, device grade 6) Table 27: Available M95640x products (package, voltage range, temperature grade): /PB process letter added, /P process letter removed. ...
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... DC characteristics (M95320, device grade V parameter added to DC characteristics tables 13, 14, RES Note added characteristics tables 17, 18, CLQV Note added to Table 20: AC characteristics (M95320-R) characteristics (M95640-R). Process letter modified in 64 Kbit densities removed from datasheet. ECOPACK status of packages specified in Ordering information scheme and I added to ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...