CY7C1338G-117AXC Cypress Semiconductor Corp, CY7C1338G-117AXC Datasheet - Page 4

• Manufacturer Part Number: CY7C1338G-117AXC
• Description: IC SRAM 4MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1338G-117AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05521 Rev. *A
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
ADSP
ADSC
ZZ
DQs
V
V
V
V
MODE
NC
DD
SS
DDQ
SSQ
Name
Synchronous
Synchronous
Asynchronous
Synchronous
C0
I/O Ground Ground for the I/O circuitry.
I/O Power
Ground
) is 6.5 ns (133-MHz device).
Supply
Supply
Power
Input-
Input-
Input-
Input-
Static
I/O-
I/O
(continued)
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE . When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die.
[A:D]
) inputs. A Global Write
1
, CE
2
®
, CE
and i486™
PRELIMINARY
3
) and an
1
1
is deasserted HIGH
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP is ignored if CE
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
BWC controls DQ
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Description
C
, and BW
A
controls DQ
1
is HIGH.
A:D
D
1
])are ignored during this first
, CE
controls DQ
1
A
, CE
2
and BWB controls DQ
, CE
CY7C1338G
[1:0]
2
, and CE
3
are also loaded
are all asserted
D
CDV
. All I/Os are
Page 4 of 17
DD
after clock
3
[1:0]
or left
are all
are
B
.