CY7C1338G-117AXC Cypress Semiconductor Corp, CY7C1338G-117AXC Datasheet
CY7C1338G-117AXC
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CY7C1338G-117AXC Summary of contents
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... For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05521 Rev. *A PRELIMINARY Functional Description The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with ) DD minimum glue logic. Maximum access delay from clock rise is 6 ...
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... V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ Document #: 38-05521 Rev. *A PRELIMINARY 133 MHz 117 MHz 6.5 7.5 225 220 40 40 100-Pin TQFP CY7C1338G CY7C1338G 100 MHz Unit 8.0 ns 205 DDQ 76 V SSQ BYTE SSQ 70 V DDQ DDQ V 60 SSQ ...
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... DDQ ADV DDQ CLK BWE DDQ MODE DDQ Description to select/deselect the device. ADSP is ignored select/deselect the device select/deselect the device CY7C1338G DDQ DDQ DDQ DDQ DDQ , CE , and CE are sampled active and BWE). [A:D] is HIGH sampled only sampled only when a new external address is ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... OE. Burst Sequences The CY7C1338G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. ...
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... L H Next Next Next Next Current Current Current Current Current Current and BWE = L or GW= L. WRITE = H when all Byte write enable signals CY7C1338G L-H tri-state L-H tri-state L-H tri-state L-H tri-state L-H tri-state tri-state L L-H tri-state L L L-H tri-state L L-H tri-state H L ...
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... Write Bytes D, B Write Bytes Write Bytes Write All Bytes Write All Bytes Note: 7. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05521 Rev. *A PRELIMINARY [ BWE valid. Appropriate write will be done based on which byte write is active. X CY7C1338G ...
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... CYC IL (min.) within 200ms. During this time V < CY7C1338G Ambient ] Temperature V DD 3.3V −5%/+10% 2.5V –5% 0°C to +70°C –40°C to +85°C CY7C1338G Min. 3.135 2.375 = –4.0 mA 2.4 = –1.0 mA 2 –0.3 –0.3 −5 – ...
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... POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1338G TQFP Package BGA Package TBD TBD TBD TBD TQFP Package BGA Package Unit 5 = 3.3V ...
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... CEH Document #: 38-05521 Rev. *A PRELIMINARY [11, 12, 13, 14, 15, 16] Description Min. [12, 13, 14] [12, 13, 14] 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 CY7C1338G 133 MHz 117 MHz 100 MHz Max. Min. Max. Min 3.5 3.5 3.5 3 3.5 3.5 2 ...
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... A2 t WEH t t ADVH ADVS t CDV t OELZ t OEHZ t DOH Q(A2) Q( DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1338G ADV suspends burst Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH Deselect Cycle t CHZ ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05521 Rev. *A PRELIMINARY WES WEH DH D(A2 BURST WRITE DON’T CARE UNDEFINED [A:D] CY7C1338G ADSC extends burst t ADS t ADH A3 t WES t WEH t ADVS t ADVH ADV suspends burst D( D( D(A3) D( Extended BURST WRITE LOW. ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 20 HIGH. Document #: 38-05521 Rev. *A PRELIMINARY WEH WES OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1338G A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs UNDEFINED A6 D(A6) Page ...
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... Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1338G-133AXC CY7C1338G-133BGC CY7C1338G-133BGXC CY7C1338G-133AXI CY7C1338G-133BGI CY7C1338G-133BGXI 117 CY7C1338G-117AXC CY7C1338G-117BGC CY7C1338G-117BGXC CY7C1338G-117AXI CY7C1338G-117BGI CY7C1338G-117BGXI 100 CY7C1338G-100AXC CY7C1338G-100BGC CY7C1338G-100BGXC CY7C1338G-100AXI CY7C1338G-100BGI CY7C1338G-100BGXI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BGX package will be available in 2005 ...
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... MIN. 1.00 REF. DETAIL Document #: 38-05521 Rev. *A PRELIMINARY DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1338G 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1338G 51-85115-*B Page ...
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... Document History Page Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM Document Number: 38-05521 REV. ECN NO. Issue Date ** 224369 See ECN *A 278513 See ECN Document #: 38-05521 Rev. *A PRELIMINARY Orig. of Change RKF New data sheet VBL Deleted 66 MHz Changed TQFP to PB-Free TQFP in Ordering Info section ...