CY7C1338G-100AXC Cypress Semiconductor Corp, CY7C1338G-100AXC Datasheet
CY7C1338G-100AXC
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CY7C1338G-100AXC Summary of contents
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... Document Number: 38-05521 Rev. *F 4-Mbit (128 K × 32) Flow-through Sync Functional Description The CY7C1338G is a 128 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... Timing Diagrams ............................................................ 12 Read Cycle Timing .................................................... 12 Write Cycle Timing .................................................... 13 ZZ Mode Timing ........................................................ 15 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagrams .......................................................... 17 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC Solutions ......................................................... 21 CY7C1338G Page [+] Feedback ...
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... BYTE SSQ V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ Document Number: 38-05521 Rev. *F 133 MHz 6.5 225 40 100-pin TQFP Pinout CY7C1338G CY7C1338G 100 MHz Unit 8.0 ns 205 DDQ 76 V SSQ BYTE SSQ 70 V DDQ DDQ 60 V SSQ BYTE A 58 ...
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... CLK BWE MODE NC/72M Description , select/deselect the device. ADSP is ignored select/deselect the device sampled only when a new external address select/deselect the device sampled only when a new external address CY7C1338G DDQ NC/576M NC/9M A NC/ DDQ DDQ DDQ NC/36M DDQ , and CE are sampled active. A ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... Document Number: 38-05521 Rev. *F Burst Sequences after clock rise. CDV The CY7C1338G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on are all asserted active, MODE will select a linear burst sequence ...
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... Next Next Next Next Next Current Current Current Current Current Current and BWE = L or GW= L. WRITE = H when all byte write enable signals CY7C1338G L-H Tri-state L-H Tri-state L-H Tri-state L-H Tri-state L-H Tri-state Tri-state L L-H Tri-state L L L-H Tri-state L L-H Tri-state H L ...
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... Write all bytes Notes “Don't Care.” Logic HIGH Logic LOW. 8. Table only lists a partial listing of the byte write combinations. Any combination of BW Document Number: 38-05521 Rev BWE valid. Appropriate write will be done based on which byte write is active. X CY7C1338G Page [+] Feedback ...
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... All speeds DD V 0.3 V, – 0 /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1338G + 0 Ambient Temperature 0 °C to +70 °C 3.3 V5% / 2.5 V – 10 –40 °C to +85 °C Min Max 3.135 3 ...
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... EIA/JESD51 317 3 DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2 DDQ GND =1538 INCLUDING JIG AND (b) SCOPE CY7C1338G 119 BGA 100 TQFP Unit Max Max 100 TQFP 119 BGA Unit Package Package 30.32 34.1 °C/W 6.85 14.0 ° ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5 V. DDQ CY7C1338G –133 –100 Unit Min Max Min Max 1 – 1 – ...
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... ADVH ADVS ADV suspends burst. t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1338G Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state is HIGH LOW HIGH Page [+] Feedback ...
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... ADSC extends burst WEH WES ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. [A:D] CY7C1338G t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE is HIGH LOW HIGH Page ...
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... The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 23 HIGH. Document Number: 38-05521 Rev WEH WES OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1338G A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs is HIGH LOW HIGH Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 25. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05521 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1338G Page [+] Feedback ...
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... Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed Package (MHz) Ordering Code Diagram 100 CY7C1338G-100AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free Ordering Code Definitions CY7C 1338 G - 100 AX C Document Number: 38-05521 Rev. *F www.cypress.com ...
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... Package Diagrams 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05521 Rev. *F CY7C1338G 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 38-05521 Rev. *F 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 CY7C1338G 51-85115 *C Page [+] Feedback ...
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... WE write enable Document Number: 38-05521 Rev. *F Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mm milli meter ms milli seconds MHz Mega Hertz pF pico Farad W Watts °C degree Celcius CY7C1338G Page [+] Feedback ...
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... Document History Page Document Title: CY7C1338G 4-Mbit (128 K × 32) Flow-through Sync SRAM Document Number: 38-05521 Orig. of REV. ECN NO. Issue Date Change ** 224369 See ECN *A 278513 See ECN *B 333626 See ECN *C 418633 See ECN *D 480368 See ECN *E 2896584 03/20/2010 *F 3036754 09/23/2010 Document Number: 38-05521 Rev. *F ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05521 Rev. *F Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised September 23, 2010 CY7C1338G PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...