NAND01GW3A0AN6E STMicroelectronics, NAND01GW3A0AN6E Datasheet - Page 20

IC FLASH 1GBIT 48TSOP

NAND01GW3A0AN6E

Manufacturer Part Number
NAND01GW3A0AN6E
Description
IC FLASH 1GBIT 48TSOP
Manufacturer
STMicroelectronics
Datasheet

Specifications of NAND01GW3A0AN6E

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
1G (128M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Speed
-
Other names
497-3611

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Bus operations
4.4
4.5
4.6
20/64
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
Bus Cycle
Command Input
Bus Operation
Address Input
Write Protect
Data Output
Data Input
5
Figure 26
Standby
2
3
4
1
th(2)
nd
st
rd
th
(1)
Bus Operations
Address Insertion, x8 Devices
and
IH
I/O7
A19
A27
V
V
A7
when issuing a program or erase command.
IL
IL
Table 25
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
I/O6
A18
A26
V
AL
V
V
V
A6
V
V
X
X
IH
IL
IL
IL
IL
IL
for details of the timings requirements.
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O5
A17
A25
V
V
A5
IL
IL
Fallin
V
V
V
R
X
X
g
IH
IH
IH
I/O4
A16
A24
V
V
A4
Rising
Rising
Rising
IL
IL
V
W
X
X
IH
V
I/O3
WP
X
A11
A15
A23
IL
V
V
V
A3
X
X
D
(2)
IH
/V
IL
IL
D
Data Output
I/O0 - I/O7
Command
Data Input
NAND01G-B, NAND02G-B
Address
I/O2
A10
A14
A22
V
A2
IL
X
X
I/O1
A13
A21
V
A1
A9
IL
I/O8 - I/O15
Data Output
Data Input
X
X
X
X
I/O0
A12
A20
A28
A0
A8
(1)

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