CY7C1370C-167BGC Cypress Semiconductor Corp, CY7C1370C-167BGC Datasheet - Page 8

• Manufacturer Part Number: CY7C1370C-167BGC
• Description: IC SRAM 18MBIT 167MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1370C-167BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05233 Rev. *D
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1370C and CY7C1372C are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQ
CY7C1372C) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DQP (DQ
DQP
CY7C1372C) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1370C/CY7C1372C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE
WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
CY7C1372C) inputs must be driven in each cycle of the burst
write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQ
a,b,c,d
a,b,c,d
Parameter
/DQP
for
Operation
[1, 2, 3, 4, 5, 6, 7]
a,b,c,d
CY7C1370C
for CY7C1370C and DQ
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
a,b,c,d
[a:d]
for CY7C1370C and BW
. See Write Cycle Description table for details.
Description
and
None
None
External
Next
External
Next
External
Next
1
Address
, CE
DQ
Used
2
a,b
, and CE
a,b
s
/DQP
=data when OE is active.
/DQP
CE
H
X
X
X
X
L
L
L
a,b
3
a,b
a,b
a,b,c,d
) and
for
for
for
ZZ
L
L
L
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
/
ADV/LD
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
DD
DD
H
H
H
H
L
L
L
L
Address
− 0.2V
Test Conditions
− 0.2V
Address
A1,A0
First
A1,A0
First
00
01
10
11
00
01
10
11
WE
H
X
X
H
X
X
X
L
BW
X
X
X
X
X
X
L
L
Address
Second
ZZREC
A1,A0
Address
x
Second
01
10
00
A1,A0
11
1
, CE
01
00
11
10
OE
after the ZZ input returns LOW.
X
X
H
H
X
X
L
L
2
, and CE
DD
CEN
)
2t
L
L
L
L
L
L
L
L
Address
s
Min.
and DQP
A1,A0
Third
CYC
Address
0
A1,A0
10
00
01
11
Third
3
, must remain inactive
10
00
01
11
CLK
CY7C1370C
CY7C1372C
L-H Three-State
L-H Three-State
L-H Data Out (Q)
L-H Data Out (Q)
L-H Three-State
L-H Three-State
L-H Data In (D)
L-H Data In (D)
[a:d]
2t
2t
Max
= Three-state when
60
CYC
CYC
Page 8 of 27
Address
Address
Fourth
A1,A0
Fourth
A1,A0
DQ
11
00
01
10
11
10
01
00
Unit
mA
ns
ns
ns
ns