CY7C1370C-167AC Cypress Semiconductor Corp, CY7C1370C-167AC Datasheet
CY7C1370C-167AC
Specifications of CY7C1370C-167AC
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CY7C1370C-167AC Summary of contents
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... Document #: 38-05233 Rev. *D 512K x 36/ Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states ...
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... AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control CY7C1370C-250 CY7C1370C-225 CY7C1372C-250 CY7C1372C-225 2.6 2.8 350 325 70 70 CY7C1370C CY7C1372C DQs DQP DQP INPUT E E REGISTER 0 CY7C1370C-200 CY7C1370C-167 CY7C1372C-200 CY7C1372C-167 Unit 3.0 3.4 ns 300 275 Page [+] Feedback ...
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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1370C CY7C1372C DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa 59 DQa DDQ ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ E(72 DDQ Document #: 38-05233 Rev. *D 119-ball BGA Pinout CY7C1370C (512K × 36) – 14 × 22 BGA ADV/ DQP CLK CEN DQP MODE E(72 TMS TDI TCK TDO CY7C1372C (1M x 18)– BGA ...
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... Pin Configurations (continued) CY7C1370C (512K × 36) – 13 × 15 fBGA E(288 CE2 C DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC E(72 MODE E(36 E(288 CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC ...
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... The direction of the pins is [17:0] –DQ are placed in a three-state condition. The outputs are controlled DQP is controlled controlled CY7C1370C CY7C1372C and DQP , BW controls DQ and DQP , During [31:0] , DQP is controlled ...
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... Burst Read Accesses The CY7C1370C and CY7C1372C have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ...
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... Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1370C and CY7C1372C are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted ...
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... Operation NOP/WRITE ABORT (Begin Burst) None WRITE ABORT (Continue Burst) Next IGNORE CLOCK EDGE (Stall) Current SNOOZE MODE None Partial Write Cycle Description Function (CY7C1370C) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370C/CY7C1372C incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. Document #: 38-05233 Rev. *D CY7C1370C CY7C1372C When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register ...
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... TEST-LOGIC/ 0 IDLE Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05233 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1370C CY7C1372C 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... DDQ GND ≤ V ≤ DDQ GND ≤ V ≤ DDQ [12, 13] Over the Operating Range Description (AC) > −0.5V for t < t /2. IL TCYC / ns CY7C1370C CY7C1372C Selection Circuitry TDO Min. Max. = 3.3V 2.4 = 2.5V 1.7 = 3.3V 2.9 = 2.5V 2.1 = 3.3V 0.4 = 2.5V 0.4 = 3.3V ...
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... TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05233 Rev. *D [12, 13] Over the Operating Range (continued) Description 2. 1 TCYC t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX CY7C1370C CY7C1372C Min. Max. Unit ALL INPUT PULSES 1.25V 1.5 ns Page [+] Feedback ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05233 Rev. *D CY7C1372C 010 010 Reserved for version number. 01010001000010101 Reserved for future use. 00000110100 Allows unique identification of SRAM vendor Indicate the presence register. Bit Size (x36 Description CY7C1370C CY7C1372C Description Page [+] Feedback ...
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... BGA Boundary Scan Orde CY7C1370C (512K x 36) Bit# Ball ID Bit CY7C1372C (1M x 18) Bit# Ball ID Bit Document #: 38-05233 Rev Ball Not Bonded T3 (Preset Not Bonded R3 (Preset Not Bonded P1 (Preset Not Bonded 20 (Preset Not Bonded D2 (Preset Not Bonded A3 (Preset Not Bonded (Preset to 0) ...
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... Boundary Scan Order CY7C1370C (512K x 36) Bit# Ball ID Bit B10 43 9 A10 44 10 C11 45 11 E10 46 12 F10 47 13 G10 48 14 D10 49 15 D11 50 16 E11 51 17 F11 52 18 G11 53 19 H11 54 20 J10 55 21 K10 56 22 L10 57 23 ...
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... All speed grades DD ≥ V ≤ /2), undershoot: V (AC)> -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1370C CY7C1372C Ambient Temperature DDQ 0°C to +70°C 3.3V–5%/+10% 2.5V – Min. Max. 3.135 3.6 3.135 V DD 2.375 2.625 2.4 2 ...
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... SRAMs when sharing the same EOLZ CHZ CLZ 2.5V. DDQ= CY7C1370C CY7C1372C fBGA Max. TQFP Max. Unit [16] ALL INPUT PULSES 90% 90% 1.25V 10% 10% < ...
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... CLZ D(A1) D(A2) D(A2+1) Q(A3) t BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1370C CY7C1372C -200 -167 Unit 1.4 1.5 ns 1.4 1.5 ns 1.4 1.5 ns 1.4 1.5 ns 1.4 1.5 ns 1.4 1 ...
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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05233 Rev. *D [23,24,26 D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE High-Z DON’T CARE CY7C1370C CY7C1372C CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI ...
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... CY7C1370C-225AC CY7C1372C-225AC CY7C1370C-225BGC CY7C1372C-225BGC CY7C1370C-225BZC CY7C1372C-225BZC 200 CY7C1370C-200AC CY7C1372C-200AC CY7C1370C-200BGC CY7C1372C-200BGC CY7C1370C-200BZC CY7C1372C-200BZC 167 CY7C1370C-167AC CY7C1372C-167AC CY7C1370C-167BGC CY7C1372C-167BGC CY7C1370C-167BZC CY7C1372C-167BZC Document #: 38-05233 Rev. *D Package Name Package Type A101 100-lead Thin Quad Flat Pack ( 1.4 mm) BG119 119-ball Ball Grid Array ( 2.4 mm) BB165A 165-ball Fine Pitch Ball Grid Array ( ...
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... CY7C1372C-225BGI CY7C1370C-225BZI CY7C1372C-225BZI 200 CY7C1370C-200AI CY7C1372C-200AI CY7C1370C-200BGI CY7C1372C-200BGI CY7C1370C-200BZI CY7C1372C-200BZI 167 CY7C1370C-167AI CY7C1372C-167AI CY7C1370C-167BGI CY7C1372C-167BGI CY7C1370C-167BZI CY7C1372C-167BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05233 Rev. *D Package Name Package Type A101 100-lead Thin Quad Flat Pack ( ...
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... MAX. 0.60±0.15 0.20 MIN. 1.00 REF. A DETAIL Document #: 38-05233 Rev. *D DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 12°±1° TYP. (8X STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. CY7C1370C CY7C1372C 1.40±0.05 A SEE DETAIL 0.20 MAX. 1.60 MAX. 51-85050-*A Page [+] Feedback ...
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... Package Diagrams (continued) 119 Lead PBGA ( 2.4 mm) BG119 Document #: 38-05233 Rev. *D CY7C1370C CY7C1372C 51-85115-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1370C CY7C1372C 51-85122-*C ...
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... Document History Page Document Title: CY7C1370C/CY7C1372C 512K x 36/ Pipelined SRAM with NoBL™ Architecture Document Number: 38-05233 REV. ECN No. Issue Date ** 116273 08/27/02 *A 121536 11/21/02 *B 206100 see ECN *C 225487 See ECN *D 231349 See ECN Document #: 38-05233 Rev. *D Orig. of Change Description of Change ...