M48Z35AV-10MH6E STMicroelectronics, M48Z35AV-10MH6E Datasheet - Page 6

• Manufacturer Part Number: M48Z35AV-10MH6E
• Description: IC NVSRAM 256KBIT 100NS 28SOIC
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z35AV-10MH6E

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 100ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOH
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2881-5; M48Z35AV-10MH6

M48Z35AY, M48Z35AV
OPERATING MODES
The M48Z35AY/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single power supply for an out of tolerance
condition. When V
write protects the SRAM, providing a high degree
Table 2. Operating Modes
Note: X = V
READ Mode
The M48Z35AY/V is in the READ Mode whenever
W (WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
6/21
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
1. See
IH
A0-A14
E
G
DQ0-DQ7
Table 10., page 14
or V
IL
; V
V
SO
CC
SO
= Battery Back-up Switchover Voltage.
4.5 to 5.5V
3.0 to 3.6V
to V
is out of tolerance, the circuit
V
V
PFD
or
for details.
SO
CC
(1)
(min)
AVQV
(1)
) after the last
tAVQV
tELQX
tELQV
tGLQX
tGLQV
V
V
V
V
E
X
X
IH
IL
IL
IL
tAVAV
VALID
V
V
G
X
X
X
X
IH
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below approximately V
nects the battery which maintains data until valid
power returns.
IL
available after the latter of the Chip Enable Access
time (t
(t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
Address Access.
GLQV
AXQX
).
ELQV
V
V
V
W
X
X
X
IH
IH
IL
AVQV
) but will go indeterminate until the next
VALID
) or Output Enable Access time
, the data lines will be driven to an
DQ0-DQ7
High Z
High Z
High Z
High Z
D
D
OUT
tGHQZ
IN
SO
, the control circuitry con-
AVQV
Battery Back-up Mode
. If the Address In-
CMOS Standby
tAXQX
tEHQZ
CC
Standby
Power
AI00925
Active
Active
Active
. As V
CC
falls