M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 27

• Manufacturer Part Number: M25P05-AVMN6T
• Description: IC FLASH 512KBIT 40MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 40MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1621-2

POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
– V
– V
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write
operations during power-up, a Power On Reset
(POR) circuit is included. The logic inside the
device is held reset while V
Power On Reset (POR) threshold voltage, V
all operations are disabled, and the device does
not respond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
elapsed after the moment that V
V
the device is not guaranteed if, by this time, V
still below V
Program or Erase instructions should be sent until
the later of:
Figure 21. Power-up Timing
WI
lay of t
CC
SS
threshold. However, the correct operation of
V CC (max)
V CC (min)
(min) at Power-up, and then for a further de-
at Power-down
VSL
V WI
V CC
CC
(min). No Write Status Register,
Reset State
Device
of the
Program, Erase and Write Commands are Rejected by the Device
CC
Chip Selection Not Allowed
) until V
CC
CC
is less than the
CC
rises above the
reaches the
PUW
CC
WI
has
is
–
tPUW
tVSL
– t
– t
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
At Power-up, the device is in the following state:
– The device is in the Standby mode (not the
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabilize the V
device in a system should have the V
decoupled by a suitable capacitor close to the
package pins. (Generally, this capacitor is of the
order of 0.1µF).
At Power-down, when V
operating voltage, to below the Power On Reset
(POR) threshold voltage, V
disabled and the device does not respond to any
instruction. (The designer needs to be aware that
if a Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Deep Power-down mode).
PUW
VSL
Read Access allowed
after V
after V
CC
(min), the device can be selected for
VSL
CC
CC
, has elapsed, after V
passed the V
passed the V
Device fully
accessible
WI
CC
Table 8.
CC
PUW
, all operations are
WI
CC
time
drops from the
(min) level
threshold
delay is not yet
supply. Each
CC
M25P05-A
AI04009C
has risen
CC
27/42
rail